 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| this is information on a product in full production. june 2015 docid025118 rev 5 1/106 STM8AF6213 stm8af6223 stm8af6223a stm8af6226 automotive 8-bit mcu, with up to 8 kbyte flash, data eeprom, 10-bit adc, timers, lin, spi, i2c, 3 to 5.5 v datasheet - production data features ? core ?max f cpu : 16 mhz ? advanced stm8a core with harvard architecture and 3-stage pipeline ? extended instruction set ? memories ? program memory: 4 to 8 kbyte flash program; data retention 20 years at 55 c after 1 kcycle ? data memory: 640 byte true data eeprom; endurance 300 kcycle ? ram: 1 kbyte ? clock management ? low-power crystal re sonator oscillator with external clock input ? internal, user-trimmable 16 mhz rc and low-power 128 khz rc oscillators ? clock security system with clock monitor ? reset and supply management ? wait/auto-wakeup/halt low-power modes with user definable clock gating ? low-consumption power-on and power- down reset ? interrupt management ? nested interrupt controller with 32 interrupts ? up to 28 external interrupts on 7 vectors ? timers ? advanced control timer: 16-bit, 4 capcom channels, 3 complementary outputs, dead- time insertion and flex ible synchronization ? 16-bit general purpose timer with 3 capcom channels each (ic, oc, pwm) ? 8-bit ar basic timer with 8-bit prescaler ? auto-wakeup timer ? window and independent watchdog timers ? i/os ? up to 28 i/os on a 32-pin package including 21 high sink outputs ? highly robust i/o design, immune against current injection ? communication interfaces ? linuart lin 2.2 compliant, master/slave modes with automatic resynchronization ? spi interface up to 8 mbit/s or f master /2 ?i 2 c interface up to 400 kbit/s ? analog to digital converter (adc) ? 10-bit, 1 lsb adc with up to 7 muxed channels + 1 internal channel, scan mode and analog watchdog ? internal reference voltage measurement ? operating temperature up to 150 c ? qualification conforms to aec-q100 rev g lqfp32 7x7 mm tssop20 (6.4x4.4 mm) www.st.com
contents STM8AF6213/23/23a/26 2/106 docid025118 rev 5 contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4 product overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.1 central processing unit (cpu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.1.1 architecture and registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.1.2 addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.1.3 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.2 single wire interface module (swim) and debug module (dm) . . . . . . . . 14 4.2.1 swim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.2.2 debug module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.3 interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.4 flash program and data eeprom memory . . . . . . . . . . . . . . . . . . . . . . . 14 4.4.1 write protection (wp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.4.2 read-out protection (rop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.5 clock controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.5.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.6 power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.7 watchdog timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.8 auto wakeup counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.9 beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.10 tim1 - 16-bit advanced control timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.11 tim5 - 16-bit general purpose timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.12 tim6 - 8-bit basic timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.13 analog-to-digital converter (adc1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.14 communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.14.1 linuart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.14.2 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.14.3 inter integr ated circuit (i 2 c) interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 docid025118 rev 5 3/106 STM8AF6213/23/23a/26 contents 4 5 pinout and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.1 tssop20 pinouts and pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.2 lqfp32 pinout and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.3 alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6 memory and register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.2 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.2.1 i/o port hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.2.2 cpu/swim/debug module/interrupt contro ller registers . . . . . . . . . . . . 43 7 interrupt vector mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 8 option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 8.1 option byte description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 8.2 STM8AF6213/23/23a/26 alternate function remapping bits . . . . . . . . . . . 49 9 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 9.1 parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 9.1.1 minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 9.1.2 typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 9.1.3 typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 9.1.4 loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 9.1.5 pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 9.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 9.3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 9.3.1 vcap external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 9.3.2 supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 9.3.3 external clock sources and timing characteristics . . . . . . . . . . . . . . . . . 67 9.3.4 internal clock sources and timing characte ristics . . . . . . . . . . . . . . . . . 69 9.3.5 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 9.3.6 i/o port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 9.3.7 reset pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 9.3.8 spi serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 9.3.9 i 2 c interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 9.3.10 10-bit adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 contents STM8AF6213/23/23a/26 4/106 docid025118 rev 5 9.3.11 emc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 10 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 10.1 lqfp32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 10.2 tssop20 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 10.3 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 10.3.1 reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 10.3.2 selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . . 98 11 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 12 stm8 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 12.1 emulation and in-circuit debugging tools . . . . . . . . . . . . . . . . . . . . . . . . 101 12.1.1 stice key features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 12.2 software tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 12.2.1 stm8 toolset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 12.2.2 c and assembly toolchains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 12.3 programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 13 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 docid025118 rev 5 5/106 STM8AF6213/23/23a/26 list of tables 6 list of tables table 1. STM8AF6213/23/23a/26 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 2. peripheral clock gating bit assignments in clk_pckenr1/2 registers . . . . . . . . . . . . . . . 16 table 3. tim timer features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 4. communication peripheral naming correspondence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 5. legend/abbreviations for pinout tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 table 6. STM8AF6213/stm8af6223 tssop20 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 7. stm8af6223a tssop20 pin descripti on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 8. stm8af6226 lqfp32 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 9. memory model for the devices covered in this datas heet. . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 10. i/o port hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 11. general hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 12. cpu/swim/debug module/interrupt controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 13. interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 14. option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 15. option byte description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 16. stm8af6226 alternate functi on remapping bits [7:2] for 32-pin packages . . . . . . . . . . . . 49 table 17. STM8AF6213 and stm8af6223 alte rnate function remapping bits [7:2] ? for 20-pin packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 18. stm8af6223a alternate function remapping bits [7:2] for 20-pin packages . . . . . . . . . . . 50 table 19. stm8af6226 alternate functi on remapping bits [1:0] for 32-pin packages . . . . . . . . . . . . 51 table 20. STM8AF6213/stm8af6223 alte rnate function remapping bits [1:0] ? for 20-pin packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 21. stm8af6223a alternate function remapping bits [1:0] for 20-pin packages . . . . . . . . . . . 52 table 22. voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 23. current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 24. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 25. operating lifetime (olf) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 26. general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 27. operating conditions at power-up/power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 28. total current consumption wit h code execution in run mode at v dd = 5 v. . . . . . . . . . . . . 58 table 29. total current consumption wit h code execution in run mode at v dd = 3.3 v . . . . . . . . . . . 59 table 30. total current consumption in wait mode at v dd = 5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 31. total current consumption in wait mode at v dd = 3.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 32. total current consumption in active halt mode at v dd = 5 v . . . . . . . . . . . . . . . . . . . . . . . 61 table 33. total current consumption in active halt mode at v dd = 3.3 v . . . . . . . . . . . . . . . . . . . . . . 61 table 34. total current consum ption in halt mode at v dd = 5 v. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 35. total current consum ption in halt mode at v dd = 3.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 36. wakeup times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 37. total current consumption and ti ming in forced reset state . . . . . . . . . . . . . . . . . . . . . . . . 63 table 38. peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 39. hse user external clock characteri stics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 7 table 40. hse oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 41. hsi oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 42. lsi oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 43. ram and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 44. flash program memory/data eeprom memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 45. flash program memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 46. data memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 list of tables STM8AF6213/23/23a/26 6/106 docid025118 rev 5 table 47. i/o static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 48. output driving current (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 49. output driving current (true open drain ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 50. output driving current (high sink ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 51. nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 52. spi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 table 53. i 2 c characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 table 54. adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 55. adc accuracy with rain < 10 k ? , v dd = 5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 56. adc accuracy with rain < 10 k ? , v dd = 3.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 57. ems data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 table 58. emi data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 59. esd absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 60. electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 table 61. lqfp32 - 32-pin, 7 x 7 mm low-profile quad flat package ? mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 table 62. tssop20 ? 20-lead thin shrink sm all outline, 6.5 x 4.4 mm, 0.65 mm pitch, ? package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 table 63. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 table 64. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 docid025118 rev 5 7/106 STM8AF6213/23/23a/26 list of figures 8 list of figures figure 1. STM8AF6213/23/23a/26 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 2. flash memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 3. STM8AF6213/stm8af6223 tssop20 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 4. stm8af6223a tssop20 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 5. stm8af6226 lqfp32 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 9 figure 6. memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 7. pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 8. pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 9. f cpumax versus v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 figure 10. external capacitor c ext . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 11. typ i dd(run) vs. v dd hse user external clock, f cpu = 16 mhz . . . . . . . . . . . . . . . . . . . . . 64 figure 12. typ i dd(run) vs. f cpu hse user external clock, v dd = 5 v . . . . . . . . . . . . . . . . . . . . . . . . 64 figure 13. typ i dd(run) vs. v dd hsei rc osc., f cpu = 16 mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 figure 14. typ i dd(wfi) vs. v dd hse user external clock, f cpu = 16 mhz . . . . . . . . . . . . . . . . . . . . . 65 figure 15. typ i dd(wfi) vs. f cpu hse user external clock, v dd = 5 v . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 16. typ i dd(wfi) vs. v dd hsi rc osc., f cpu = 16 mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 17. hse external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 figure 18. hse oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 figure 19. typical v il and v ih vs v dd @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 figure 20. typical pull-up resistance r pu vs v dd @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . 73 figure 21. typical pull-up current i pu vs v dd @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 22. typ. v ol @ v dd = 5 v (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 figure 23. typ. v ol @ v dd = 3.3 v (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 figure 24. typ. v ol @ v dd = 5 v (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 figure 25. typ. v ol @ v dd = 3.3 v (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 figure 26. typ. v ol @ v dd = 5 v (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 figure 27. typ. v ol @ v dd = 3.3 v (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 figure 28. typ. v dd - v oh @ v dd = 5 v (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 figure 29. typ. v dd - v oh @ v dd = 3.3 v (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 figure 30. typ. v dd - v oh @ v dd = 5 v (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 figure 31. typ. v dd - v oh @ v dd = 3.3 v (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 figure 32. typical nrst v il and v ih vs v dd @ 4 temperatures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 figure 33. typical nrst pull-up resistance vs v dd @ 4 temperatures. . . . . . . . . . . . . . . . . . . . . . . . 80 figure 34. typical nrst pull-up current vs v dd @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . 80 figure 35. recommended reset pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 figure 36. spi timing diagram - slave mode and cpha = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 figure 37. spi timing diagram - slave mode and cpha = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 figure 38. spi timing diagram - master mode (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 figure 39. typical application with i2c bus and timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 figure 40. adc accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 figure 41. typical application with adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 figure 42. lqfp32 - 32-pin, 7 x 7 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . 92 figure 43. lqfp32 - 32-pin, 7 x 7 mm low-profile quad flat package ? recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 figure 44. lqfp32 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 figure 45. tssop20 ? 20-lead thin shrink sm all outline, 6.5 x 4.4 mm, 0.65 mm pitch, ? package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 figure 46. tssop20 ? 20-lead thin shrink sm all outline, 6.5 x 4.4 mm, 0.65 mm pitch, ? list of figures STM8AF6213/23/23a/26 8/106 docid025118 rev 5 package footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 figure 47. tssop20 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 figure 48. STM8AF6213/23/23a/26 ordering information scheme (1) (2) . . . . . . . . . . . . . . . . . . . . . . 100 docid025118 rev 5 9/106 STM8AF6213/23/23a/26 introduction 103 1 introduction the datasheet contains the description of STM8AF6213, stm8af6223, stm8af6223a and stm8af6226 features, pinout, electrical characteristics, mechanical data and ordering information. ? for complete information on the stm8a microcontroller memory, registers and peripherals, please refer to stm8s series and stm8af series 8-bit microcontrollers reference manual (rm0016). ? for information on programming, erasing and protection of the internal flash memory please refer to the stm8 flash programming manual (pm0051). ? for information on the debug and swim (s ingle wire interface module) refer to the stm8 swim communication protocol and debug module user manual (um0470). ? for information on the stm8 core, please refer to the stm8 cpu programming manual (pm0044). description STM8AF6213/23/23a/26 10/106 docid025118 rev 5 2 description the STM8AF6213, stm8af6223, stm8af6223a and stm8af6226 automotive 8-bit microcontrollers offer 4 to 8 kbyte of flash program memory, plus integrated true data eeprom. the stm8s series and stm8af series 8-bit microcontrollers reference manual (rm0016) refers to devices in this family as low-density. they provid e the following benefits: performance, robustness and reduced system cost. device performance and robustness are ensured by advanced core and peripherals made in a state-of-the-art technology, a 16 mhz clock frequency, robust i/os, independent watchdogs with separate clock source, and a cl ock security system. the system cost is reduced thanks to an integrated true data eeprom for up to ? 300 kwrite/erase cycles and a high system integratio n level with internal clock oscillators, watchdog, and brown-out reset. full documentation is offered as well as a wide choice of development tools. 2 table 1. STM8AF6213/23/23a/26 features device stm8af6226 stm8af6223 stm8af6223a STM8AF6213 pin count 32 20 max. number of gpios 28 including 21 high-sink i/os 16 including 12 high-sink i/os ext. interrupt pins 28 16 timer capcom channels 6 7 6 7 timer complementary outputs 3121 a/d converter channels 7 5 7 5 low-density flash program memory (byte) 8 k 4 k data eeprom (byte) 640 (1) 1. no read-while-write (rww) capability ram (byte) 1 k peripheral set multipurpose timer (tim1), spi, i2c, linuart, window wdg, independent wdg, adc, pwm time r (tim5), 8-bit timer (tim6) docid025118 rev 5 11/106 STM8AF6213/23/23a/26 block diagram 103 3 block diagram figure 1. STM8AF6213/23/23a/26 block diagram ; 7 $ / 0 + ] 5 & l q w 0 + ] 5 & l q w n + ] 6 7 0 f r u h ' h e x j 6 : , 0 6 3 , e l w e d v l f w l p h u 7 , 0 5 h v h w e o r f n 5 h v h w 3 2 5 % 2 5 & o r f n f r q w u r o o h u ' h w h f w r u & o r f n w r s h u l s k h u d o v d q g f r u h 0 e l w v $ g g u h v v d q g g d w d e x v : l q g r z : ' * 8 s w r . e \ w h s u r j u d p ) o d v k e \ w h . e \ w h 5 $ 0 $ ' & 5 h v h w . e l w v 6 l q j o h z l u h g h e x j l q w h u i d f h e l w d g y d q f h g f r q w u r o w l p h u 7 , 0 e l w j h q h u d o s x u s r v h w l p h u v 7 , 0 g d w d ( ( 3 5 2 0 , q g h s h q g h q w : ' * & $ 3 & 2 0 f k d q q h o v 8 s w r 8 s w r f k d q q h o v , & $ : 8 w l p h u / , 1 8 $ 5 7 / , 1 6 3 , h p x o 0 6 9 n + ] e h h s % h h s h u 8 s w r & $ 3 & 2 0 f k d q q h o v f r p s o h p h q w d u \ r x w s x w v block diagram STM8AF6213/23/23a/26 12/106 docid025118 rev 5 1. legend: ? adc: analog-to-digital converter ? becan: controller area network ? bor: brownout reset ? i2c: inter-integrated circuit multimaster interface ? iwdg: independent window watchdog ? linuart: local interconnect network unive rsal asynchronous receiver transmitter ? por: power on reset ? spi: serial peripheral interface ? swim: single wire interface module ? usart: universal synchronous as ynchronous receiver transmitter ? window wdg: window watchdog docid025118 rev 5 13/106 STM8AF6213/23/23a/26 product overview 103 4 product overview the following section intends to give an over view of the basic feat ures of the products covered by this datasheet. for more detailed information on each feature please refer to stm8s series and stm8af series 8-bit microcontrollers reference manual (rm0016). 4.1 central process ing unit (cpu) the 8-bit stm8 core is designed for code efficiency and performance. it contains 6 internal registers which are directly addressable in each execution context, 20 addressing modes including indexed indirect an d relative addressing and 80 instructions. 4.1.1 architecture and registers ? harvard architecture ? 3-stage pipeline ? 32-bit wide program memory bus - single cycle fetching for most instructions ? x and y 16-bit index registers, enabling indexed addressing modes with or without offset and read-modify-write type data manipulations ? 8-bit accumulator ? 24-bit program counter - 16-mbyte linear memory space ? 16-bit stack pointer - access to a 64 kbyte level stack ? 8-bit condition code register - 7 condition fl ags for the result of the last instruction. 4.1.2 addressing ? 20 addressing modes ? indexed indirect addressing mode for look-up tables located anywhere in the address space ? stack pointer relative addressing mode for local variables and parameter passing 4.1.3 instruction set ? 80 instructions with 2-byte average instruction size ? standard data movement and logic/arithmetic functions ? 8-bit by 8-bit multiplication ? 16-bit by 8-bit and 16-bit by 16-bit division ? bit manipulation ? data transfer between stack and accumu lator (push/pop) with direct stack access ? data transfer using the x and y registers or direct memory-to-memory transfers product overview STM8AF6213/23/23a/26 14/106 docid025118 rev 5 4.2 single wire interface module (swim) and debug module (dm) the single wire interface module together with an integrated debug module permit non- intrusive, real-time in-c ircuit debugging and fast memory programming. 4.2.1 swim single wire interface module for direct access to the debug mode and memory programming. the interface can be activated in all device operation modes.the maximum data transmission speed is 145 byte/ms. 4.2.2 debug module the non-intrusive debugging module features a performance close to a full-featured emulator. besides memory and peripheral operation, cpu operation can also be monitored in real-time by means of shadow registers. ? r/w to ram and peripheral registers in real-time ? r/w access to all resour ces by stalling the cpu ? breakpoints on all program-memory instructions (software breakpoints) ? two advanced breakpoints, 23 predefined breakpoint configurations 4.3 interrupt controller ? nested interrupts with three software priority levels ? 32 interrupt vectors with hardware priority ? up to 28 external interrupts on 7 vectors including tli ? trap and reset interrupts 4.4 flash program and data eeprom memory ? up to 8 kbyte of flash program single voltage flash memory ? 640 byte true data eeprom ? user option byte area 4.4.1 write protection (wp) write protection of flash program memory and data eeprom is provided to avoid unintentional overwriting of me mory that could result from a user software malfunction. there are two levels of write protection. the first level is known as mass (memory access security system). mass is always enabled and protects the main flash program memory, data eeprom and option byte. to perform in-application programming (iap), this write protection can be removed by writing a mass key sequence in a control register. this allows the application to write to data eeprom, modify the conten ts of main program memory or the device option byte. a second level of write protection, can be en abled to further protect a specific area of memory known as ubc (user boot code ). refer to the figure below. docid025118 rev 5 15/106 STM8AF6213/23/23a/26 product overview 103 the size of the ubc is programmable through the ubc option byte, in increments of 1 page (64-byte block) by programming the ubc option byte in icp mode. this divides the program memory into two areas: ? main program memory: up to 8 kbyte minus ubc ? user-specific boot code (ubc): configurable up to 8 kbyte the ubc area remains write-protected during in-application programming. this means that the mass keys do not unlock the ubc area. it protects the memory used to store the boot program, specific code libraries, reset and in terrupt vectors, the reset routine and usually the iap and communication routines. figure 2. flash memory organization 4.4.2 read-out protection (rop) the read-out protection blocks reading and writing the flash program memory and data eeprom memory in icp mode (and debug mode). once th e read-out protection is activated, any attempt to toggle its status triggers a global erase of the program and data memory. even if no protection can be cons idered as totally unbreakable, the feature provides a very high level of protection for a general purpose microcontroller. 0 6 9 8 % & d u h d ) o d v k s u r j u d p p h p r u \ d u h d ' d w d p h p r u \ d u h d e \ w h 5 h p d l q v z u l w h s u r w h f w h g g x u l q j , $ 3 ' d w d ( ( 3 5 2 0 p h p r u \ : u l w h d f f h v v s r v v l e o h i r u , $ 3 2 s w l r q e \ w h v 3 u r j u d p p d e o h d u h d i u r p e \ w h s d j h w r x s w r . e \ w h l q s d j h v w h s v / r z g h q v l w \ ) o d v k s u r j u d p p h p r u \ x s w r . e \ w h product overview STM8AF6213/23/23a/26 16/106 docid025118 rev 5 4.5 clock controller the clock controller distributes the system clock (f master ) coming from different oscillators to the core and the peripherals. it also manages clock gating for low-power modes and ensures clock robustness. 4.5.1 features ? clock prescaler : to get the best compromise between speed and current consumption the clock frequency to the cpu and peripherals can be adjusted by a programmable prescaler. ? safe clock switching : clock sources can be changed safely on the fly in run mode through a configuration register. the clock signal is not switched until the new clock source is ready. the design guarantees glitch-free switching. ? clock management : to reduce power consumption, the clock controller can stop the clock to the core, individual peripherals or memory. ? master clock sources: four different clock sources can be used to drive the master clock: ? 1-16 mhz high-speed external crystal (hse) ? up to 16 mhz high-speed user-external clock (hse user-ext) ? 16 mhz high-speed internal rc oscillator (hsi) ? 128 khz low-speed internal rc (lsi) ? startup clock : after reset, the microcontr oller restarts by default with an internal 2 mhz clock (hsi/8). the prescaler ratio and cloc k source can be changed by the application program as soon as the code execution starts. ? clock security system (css) : this feature can be enabled by software. if an hse clock failure occurs, the internal rc (16 mh z/8) is automatically selected by the css and an interrupt can optionally be generated. ? configurable main clock output (cco) : this outputs an external clock for use by the application. table 2. peripheral clock gating bit a ssignments in clk_pc kenr1/2 registers bit periphera l clock bit peripheral clock bit peripheral clock bit peripheral clock pcken17 tim1 pcken13 linuart pcken27 reserved pcken23 adc pcken16 tim5 pcken12 reserved pcken26 reserved pcken22 awu pcken15 reserved pcken11 spi pcken25 reserved pcken21 reserved pcken14 tim6 pcken10 i 2 c pcken24 reserved pcken20 reserved docid025118 rev 5 17/106 STM8AF6213/23/23a/26 product overview 103 4.6 power management for efficient power management , the application can be put in one of four different low- power modes. users can configure each mode to obtain the best compromise between lowest power consumption, fastest star t-up time and available wakeup sources. ? wait mode : in this mode, the cpu is stopped but peripherals are kept running. the wakeup is performed by an internal or external interrupt or reset. ? active-halt mode with regulator on : in this mode, the cpu and peripheral clocks are stopped. an internal wakeup is generated at programmable intervals by the auto wake up unit (awu). the main voltage regulator is kept powered on, so current consumption is higher than in active-halt mode with regu lator off, but the wakeup time is faster. wakeup is triggered by th e internal awu interrupt, ex ternal interrupt or reset. ? active-halt mode with regulator off : this mode is the same as active-halt with regulator on, except that the main voltage regul ator is powered off, so the wake up time is slower. ? halt mode : in this mode the microcontroller uses the least power. the cpu and peripheral clocks are stopped, the main voltage regulator is powered off. wakeup is triggered by exter nal event or reset. 4.7 watchdog timers the watchdog system is based on two independent timers providing maximum security to the applications. activation of the watchdog timers is contro lled by option bytes or by software. once activated, the watchdogs cannot be disabled by the user program without performing a reset. window watchdog timer the window watchdog is used to detect the occurrence of a software fault, usually generated by external interferences or by un expected logical conditions, which cause the application program to abandon its normal sequence. the window function can be used to trim the watchdog behavior to match the application timing perfectly. the application software must refresh the counter before time-out and during a limited time window. a reset is generated in two situations: 1. timeout: at 16 mhz cpu clock the time-out period can be adjusted between 75 s up to 64 ms. 2. refresh out of window: the downcounter is refreshed before its value is lower than the one stored in the window register. product overview STM8AF6213/23/23a/26 18/106 docid025118 rev 5 independent watchdog timer the independent watchdog peripheral can be used to resolve processor malfunctions due to hardware or software failures. it is clocked by the 128 khz lsi internal rc cloc k source, and thus stays active even in case of a cpu clock failure. the iwdg time base spans from 60 s to 1 s 4.8 auto wakeup counter ? used for auto wakeup from active halt mode ? clock source: internal 128 kh z internal low frequency rc oscillator or external clock ? lsi clock can be internally connected to tim1 input capture channel 1 for calibration 4.9 beeper the beeper function outputs a si gnal on the beep pin for sound generation. the signal is in the range of 1, 2 or 4 khz. the beeper output port is only available thro ugh the alternate function remap option bit afr7. 4.10 tim1 - 16-bit advanced control timer this is a high-end timer designed for a wi de range of control applications. with its complementary outputs, dead-tim e control and center-aligned pw m capability, the field of applications is extended to motor cont rol, lighting and half-bridge driver. ? 16-bit up, down and up/down auto-reload counter with 16-bit fractional prescaler. ? four independent capture/compare channels (capcom) configurable as input capture, output compare, pwm generation (e dge and center aligned mode) and single pulse mode output. ? synchronization module to control the timer wi th external signals or to synchronise with tim5 or tim6 ? break input to force the timer outputs into a defined state ? three complementary outputs with adjustable dead time ? encoder mode ? interrupt sources: 3 x input capture/output compare, 1 x overflow/update, 1 x break docid025118 rev 5 19/106 STM8AF6213/23/23a/26 product overview 103 4.11 tim5 - 16-bit ge neral purpose timer ? 16-bit autoreload (ar) up-counter ? 15-bit prescaler adjustable to fixed power of 2 ratios 1?32768 ? 3 individually configurable capture/compare channels ? pwm mode ? interrupt sources: 3 x input capture/output compare, 1 x overflow/update ? synchronization module to control the timer wi th external signals or to synchronize with tim1 or tim6 4.12 tim6 - 8-bit basic timer ? 8-bit autoreload, adjustable prescaler ra tio to any power of 2 from 1 to 128 ? clock source: cpu clock ? interrupt source: 1 x overflow/update ? synchronization module to control the timer wi th external signals or to synchronize with tim1 or tim5. table 3. tim timer features timer counter size (bits) prescaler counting mode capcom channels complemen tary outputs ext. trigger timer synchroniz ation/ chaining tim1 16 any integer from 1 to 65536 up/down 4 3 yes yes tim5 16 any power of 2 from 1 to 32768 up 3 0 no tim6 8 any power of 2 from 1 to 128 up 0 0 no product overview STM8AF6213/23/23a/26 20/106 docid025118 rev 5 4.13 analog-to-digita l converter (adc1) the STM8AF6213, stm8af6223, stm8af6223a and stm8af6226 products contain a 10-bit successive approximation a/d converter (a dc1) with up to 7 external and 1 internal multiplexed input channels and the following main features: ? input voltage range: 0 to v dd ? input voltage range: 0 to v dda ? conversion time: 14 clock cycles ? single and continuous and buffer ed continuous conversion modes ? buffer size (n x 10 bits) where n = number of input channels ? scan mode for single and continuous conversion of a sequence of channels ? analog watchdog capability with progra mmable upper and lower thresholds ? internal reference voltage on channel ain7 ? analog watchdog interrupt ? external trigger input ? trigger from tim1 trgo ? end of conversion (eoc) interrupt note: additional ain12 analog inpu t is not selectable in adc sca n mode or with analog watchdog. values converted from ain12 are stored only into the adc_drh/adc_drl registers. internal bandgap reference voltage channel ain7 is internally connected to the in ternal bandgap reference voltage. the internal bandgap reference is constant and can be used, for example, to monitor v dd . it is independent of variations in v dd and ambient temperature t a . 4.14 communication interfaces the following communication interfaces are implemented: ? linuart: full feature uart, synchronous mode, spi master mode, smartcard mode, irda mode, single wire mode, lin2.2 capability ? spi: full and half-duplex, 8 mbit/s ? i2c: up to 400 kbit/s some peripheral names differ between the datasheet and stm8s series and stm8af series 8-bit microcontrollers reference manual, rm0016 (see table 4 ). table 4. communication peripheral naming correspondence peripheral name in datasheet peripheral name in reference manual (rm0016) linuart uart4 docid025118 rev 5 21/106 STM8AF6213/23/23a/26 product overview 103 4.14.1 linuart main features ? 1 mbit/s full duplex sci ? spi emulation ? high precision baud rate generator ? smartcard emulation ? irda sir encoder decoder ? lin mode ? single wire half duplex mode lin mode master mode: ? lin break and delimiter generation ? lin break and delimiter detection with separate flag and interrupt source for read back checking. slave mode: ? autonomous header handling ? one single interrupt per valid header ? mute mode to filter responses ? identifier parity error checking ? lin automatic resynchronizat ion, allowing operation with internal rc oscillator (hsi) clock source ? break detection at any time, even during a byte reception ? header errors detection: ? delimiter too short ? synch field error ? deviation error (if automatic resynchronization is enabled) ? framing error in synch field or identifier field ? header time-out product overview STM8AF6213/23/23a/26 22/106 docid025118 rev 5 asynchronous communication (uart mode) ? full duplex communication - nrz standard format (mark/space) ? programmable transmit and receive baud rates up to 1 mbit/s (f cpu /16) and capable of following any standard baud rate regardless of the input frequency ? separate enable bits for transmitter and receiver ? two receiver wakeup modes: ? address bit (msb) ? idle line (interrupt) ? transmission error detection with interrupt generation ? parity control synchronous communication ? full duplex synchronous transfers ? spi master operation ? 8-bit data communication ? maximum speed: 1 mbit/s at 16 mhz (f cpu /16) 4.14.2 serial peripheral interface (spi) ? maximum speed: 8 mbit/s (f master /2) both for master and slave ? full duplex synchronous transfers ? simplex synchronous transfers on two lines with a possible bidirectional data line ? master or slave operation - selectable by hardware or software ? crc calculation ? 1 byte tx and rx buffer ? slave /master selection input pin 4.14.3 inter integrated circuit (i 2 c) interface ? i 2 c master features: ? clock generation ? start and stop generation ? i 2 c slave features: ? programmable i 2 c address detection ? stop bit detection ? generation and detection of 7-bit/10-bit addressing and general call ? supports different communication speeds: ? standard speed (up to 100 khz), ? fast speed (up to 400 khz) docid025118 rev 5 23/106 STM8AF6213/23/23a/26 pinout and pin description 103 5 pinout and pin description the following table presents the meaning of the abbreviations in use in the pin description tables in this section. 5.1 tssop20 pinouts and pin descriptions figure 3. STM8AF6213/s tm8af6223 tssop20 pinout 1. (hs) high sink capability. 2. (t) true open drain (p-buffer and protection diode to v dd not implemented). 3. [ ] alternate function remapping option (if the same al ternate function is shown twice, it indicates an exclusive choice not a dupl ication of the function). table 5. legend/abbreviations for pinout tables type i= input, o = output, s = power supply level input cm = cmos (standard for all i/os) output hs = high sink output speed o1 = slow (up to 2 mhz) ? o2 = fast (up to 10 mhz) ? o3 = fast/slow programmability with slow as default state after reset ? o4 = fast/slow programmability with fast as default state after reset port and control configuration input float = floating, wpu = weak pull-up output t = true open drain, od = open drain, pp = push pull reset state bold x (pin state after internal reset release). unless otherwise specified, the pin stat e is the same during the reset phase and after the internal reset release. 3 ' + 6 $ , 1 7 , 0 b & + $ ' & b ( 7 5 > / , 1 8 $ 5 7 b & . @ 7 , 0 b & + % ( ( 3 + 6 3 ' $ , 1 / , 1 8 $ 5 7 b 7 ; + 6 3 ' $ , 1 / , 1 8 $ 5 7 b 5 ; + 6 3 ' 1 5 6 7 2 6 & , 1 3 $ 2 6 & 2 8 7 3 $ 9 6 6 9 & $ 3 9 ' ' > 6 3 , b 1 6 6 @ 7 , 0 b & + + 6 3 $ 3 % 7 , & b 6 & / > $ ' & b ( 7 5 @ 3 & + 6 7 , 0 b & + > 7 / , @ > 7 , 0 b & + 1 @ 3 & + 6 7 , 0 b & + & / . b & & 2 $ , 1 > 7 , 0 b & + 1 @ 3 & + 6 6 3 , b 6 & . > 7 , 0 b & + @ 3 & + 6 6 3 , b 0 2 6 , > 7 , 0 b & + @ 3 & + 6 6 3 , b 0 , 6 2 > 7 , 0 b & + @ 3 ' + 6 6 : , 0 3 ' + 6 $ , 1 > 7 , 0 b & + @ 3 % 7 , & b 6 ' $ > 7 , 0 b % . , 1 @ 0 6 9 pinout and pin description STM8AF6213/23/23a/26 24/106 docid025118 rev 5 figure 4. stm8af6223a tssop20 pinout 1. (hs) high sink capability. 2. (t) true open drain (p-buffer and protection diode to v dd not implemented). 3. [ ] alternate function remapping option (if the same al ternate function is shown twice, it indicates an exclusive choice not a dupl ication of the function). 3 ' + 6 $ , 1 7 , 0 b & + $ ' & b ( 7 5 > / , 1 8 $ 5 7 b & . @ 7 , 0 b & + % ( ( 3 + 6 3 ' $ , 1 / , 1 8 $ 5 7 b 7 ; + 6 3 ' $ , 1 / , 1 8 $ 5 7 b 5 ; + 6 3 ' 1 5 6 7 2 6 & , 1 3 $ 2 6 & 2 8 7 3 $ 9 6 6 9 & $ 3 9 ' ' > 7 , 0 b % . , 1 @ , & b 6 ' $ 7 3 % 3 % + 6 7 , 0 b & + 1 $ , 1 3 % + 6 7 , 0 b & + 1 $ , 1 3 & + 6 7 , 0 b & + & / . b & & 2 $ , 1 > 7 , 0 b & + 1 @ 3 & + 6 6 3 , b 6 & . > 7 , 0 b & + @ 3 & + 6 6 3 , b 0 2 6 , > 7 , 0 b & + @ 3 & + 6 6 3 , b 0 , 6 2 > 7 , 0 b & + @ 3 ' + 6 6 : , 0 3 ' + 6 $ , 1 > 7 , 0 b & + @ 3 % 7 , & b 6 & / > $ ' & b ( 7 5 @ 0 6 9 table 6. STM8AF6213/stm8af6223 tssop20 pin description tssop pin name type input output main function (after reset) default alternate function alternate function after remap [option bit] floating wpu ext. interrupt high sink (1) speed od pp 1 pd4/ tim5_ch1/ beep [linuart_ck] i/o x x x hs o3 x x port d4 timer 5 - channel 1/beep output linuart clock [afr2] 2 pd5/ ain5/ linuart_tx i/o x x x hs o3 x x port d5 analog input 5/ linuart data transmit - 3 pd6/ ain6/ linuart_rx i/o x x x hs o3 x x port d6 analog input 6/ linuart data receive - 4 nrst i/o - x ----- reset 5 pa1/ oscin (2) i/o x x x - o1 x x port a1 resonator/ crystal in - 6 pa2/ oscout i/o x x x o1 x x port a2 resonator/ crystal out - 7 vss s - - - - - - - digital ground 8 vcap s - - - - - - - 1.8 v regulator capacitor 9 vdd s - - - - - - - digital power supply docid025118 rev 5 25/106 STM8AF6213/23/23a/26 pinout and pin description 103 10 pa3/ tim5_ch3 [spi_nss] i/o x x x hs o3 x x port a3 timer 5 channel 3 spi master/ slave select [afr1] 11 pb5/ i2c_sda [tim1_bkin] i/o x - x - o1 t (3) - port b5 i2c data timer 1 - break input [afr4] 12 pb4/ i2c_scl [adc_etr] i/o x - x - o1 t (3) - port b4 i2c clock adc external trigger [afr4] 13 pc3/ tim1_ch3/[tli]/[ tim1_ch1n] i/o x x x hs o3 x x port c3 timer 1 - channel 3 to p l e v e l interrupt [afr3] timer 1 inverted channel 1 [afr7] 14 pc4/ tim1_ch4/ clk_cco/ain2/[ tim1_ch2n] i/o x x x hs o3 x x port c4 timer 1 - channel 4 /configurabl e clock output analog input 2 [afr2]time r 1 inverted channel 2 [afr7] 15 pc5/spi_sck [tim5_ch1] i/o x x x hs o3 x x port c5 spi clock timer 5 channel 1 [afr0] 16 pc6/ spi_mosi [tim1_ch1] i/o x x x hs o3 x x port c6 pi master out/slave in timer 1 channel 1 [afr0] 17 pc7/ spi_miso [tim1_ch2] i/o x x x hs o3 x x port c7 spi master in/ slave out timer 1 channel 2[afr0] 18 pd1/ swim (4) i/o x x x hs o4 x x port d1 swim data interface - table 6. STM8AF6213/stm8af6223 tssop20 pin description (continued) tssop pin name type input output main function (after reset) default alternate function alternate function after remap [option bit] floating wpu ext. interrupt high sink (1) speed od pp pinout and pin description STM8AF6213/23/23a/26 26/106 docid025118 rev 5 19 pd2/ain3 [tim5_ch3] i/o x x x hs o3 x x port d2 - analog input 3 [afr2] timer 52 - channel 3 [afr1] 20 pd3/ ain4/ tim5_ch2/ adc_etr i/o x x x hs o3 x x port d3 analog input 4 timer 52 - channel 2/adc external trigger - 1. i/o pins used simultaneously for high curre nt source/sink must be uniformly sp aced around the package. in addition, the total driven current must respect the absolute maximum ratings ( see section: absolute maximum ratings ). 2. when the mcu is in halt/active-halt mode, pa1 is automa tically configured in input w eak pull-up and cannot be used for waking up the device. in this mode, the output state of pa1 is not driven. it is recommended to use pa1 only in input mode if halt/active-halt is used in the application. 3. in the open-drain output column, ?t? defines a true open-drai n i/o (p-buffer, weak pull-up, and protection diode to vdd are not implemented) 4. the pd1 pin is in input pull-up during the re set phase and after internal reset release. table 7. stm8af6223a tssop20 pin description tssop pin name type input output main function (after reset) default alternate function alternate function after remap [option bit] floating wpu ext. interrupt high sink (1) speed od pp 1 pd4/ tim5_ch1/ beep/spi_nss [linuart_ck] i/o x x x hs o3 x x port d4 timer 5 - channel 1/beep output linuart clock [afr2] 2 pd5/ ain5/ linuart_tx i/o x x x hs o3 x x port d5 analog input 5/ linuart data transmit - table 6. STM8AF6213/stm8af6223 tssop20 pin description (continued) tssop pin name type input output main function (after reset) default alternate function alternate function after remap [option bit] floating wpu ext. interrupt high sink (1) speed od pp docid025118 rev 5 27/106 STM8AF6213/23/23a/26 pinout and pin description 103 3 pd6/ ain6/ linuart_rx i/o x x x hs o3 x x port d6 analog input 6/ linuart data receive - 4 nrst i/o - x ----- reset - 5 pa1/ oscin (2) i/o x x x - o1 x x port a1 resonator/ crystal in - 6 pa2/ oscout i/o x x x - o1 x x port a2 resonator/ crystal out - 7 vss s ------- digital ground - 8 vcap s -------1.8 v r egulator capacitor - 9 vdd s ------- digital power supply - 10 pb5/ i2c_sda [tim1_bkin] i/o x x x - o1 t (3) x port a5 i2c data timer 1 - break input [afr4] 11 pb4/ i2c_scl [adc_etr] i/o x - x -o1t (3) - port b4 i2c clock adc external trigger [afr4] 12 pb1/ tim1_ch2n/ ain1 i/o x x x hs o3 x x port b1 timer 1 - inverted channel 2/analog input 1 - 13 pb0/ tim1_ch1n/ain0 i/o x x x hs o3 x x port b0 timer 1 - inverted channel 1/analog input 0 - 14 pc4/ tim1_ch4/ clk_cco/ain2/[ tim1_ch2] i/o x x x hs o3 x x port c4 timer 1 - channel 4 /configurabl e clock output analog input 2 [afr2]time r 1 channel 2 [afr7] 15 pc5/spi_sck [tim5_ch1] i/o x x x hs o3 x x port c5 spi clock timer 5 channel 1 [afr0] table 7. stm8af6223a tssop20 pin description (continued) tssop pin name type input output main function (after reset) default alternate function alternate function after remap [option bit] floating wpu ext. interrupt high sink (1) speed od pp pinout and pin description STM8AF6213/23/23a/26 28/106 docid025118 rev 5 16 pc6/ spi_mosi [tim1_ch1] i/o x x x hs o3 x x port c6 pi master out/slave in timer 1 channel 1 [afr0] 17 pc7/ spi_miso [tim1_ch2] i/o x x x hs o3 x x port c7 spi master in/ slave out timer 1 channel 2[afr0] 18 pd1/ swim (4) i/o x x x hs o4 x x port d1 swim data interface - 19 pd2/ain3/ tli[tim5_ch3] i/o x x x hs o3 x x port d2 - analog input 3 [afr2] timer 5 - channel 3 [afr1] 20 pd3/ ain4/ tim5_ch2/ adc_etr i/o x x x hs o3 x x port d3 analog input 4 timer 52 - channel 2/adc external trigger - 1. i/o pins used simultaneously for high curre nt source/sink must be uniformly sp aced around the package. in addition, the total driven current must respect the absolute maximum ratings ( see section: absolute maximum ratings ). 2. when the mcu is in halt/active-halt mode, pa1 is automati cally configured in input weak pull-up and cannot be used for waking up the device. in this mode, the output state of pa1 is not driven. it is recommended to use pa1 only in input mode if halt/active-halt is us ed in the application. 3. in the open-drain output column, ?t? defines a true open-drain i/o (p-buffer, weak pull-up, and protection diode to vdd are not implemented). 4. the pd1 pin is in input pull-up during the reset phase and after internal reset release. table 7. stm8af6223a tssop20 pin description (continued) tssop pin name type input output main function (after reset) default alternate function alternate function after remap [option bit] floating wpu ext. interrupt high sink (1) speed od pp docid025118 rev 5 29/106 STM8AF6213/23/23a/26 pinout and pin description 103 5.2 lqfp32 pinout and pin description figure 5. stm8af6226 lqfp32 pinout 1. (hs) high sink capability. 2. (t) true open drain (p-buffer and protection diode to v dd not implemented). 3. [ ] alternate function remapping option (if the same al ternate function is shown twice, it indicates an exclusive choice not a dupl ication of the function). > $ ' & b ( 7 5 @ , & b 6 & / 7 3 % 7 , 0 b ( 7 5 $ , 1 + 6 3 % 7 , 0 b & + 1 $ , 1 + 6 3 % 7 , 0 b & + 1 $ , 1 + 6 3 % 7 , 0 b & + 1 $ , 1 + 6 3 % 3 % 3 % > 7 , 0 b % . , 1 @ , & b 6 ' $ 7 3 % 9 & $ 3 9 ' ' > / , 1 8 $ 5 7 b 7 ; @ > 6 3 , b 1 6 6 @ 7 , 0 b & + + 6 3 $ > / , 1 8 $ 5 7 b 5 ; @ 3 ) 1 5 6 7 2 6 & , 1 3 $ 2 6 & 2 8 7 3 $ 9 6 6 3 & + 6 7 , 0 b & + > 7 / , @ > 7 , 0 b & + 1 @ 3 & + 6 7 , 0 b & + > 7 , 0 b & + 1 @ 3 & + 6 7 , 0 b & + / , 1 8 $ 5 7 b & . > 7 , 0 b & + 1 @ 3 ( 6 3 , b 1 6 6 > 7 , 0 b & + 1 @ 3 & + 6 6 3 , b 0 , 6 2 > 7 , 0 b & + @ 3 & + 6 6 3 , b 0 2 6 , > 7 , 0 b & + @ 3 & + 6 6 3 , b 6 & . > 7 , 0 b & + @ 3 & + 6 7 , 0 b & + & / . b & & 2 > $ , 1 @ > 7 , 0 b & + 1 @ 3 ' + 6 $ , 1 7 , 0 b & + $ ' & b ( 7 5 3 ' + 6 > $ , 1 @ > 7 , 0 b & + @ 3 ' + 6 6 : , 0 3 ' + 6 7 , 0 b % . , 1 > & / . b & & 2 @ 3 ' + 6 7 / , > 7 , 0 b & + @ 3 ' + 6 $ , 1 / , 1 8 $ 5 7 b 5 ; 3 ' + 6 $ , 1 / , 1 8 $ 5 7 b 7 ; 3 ' + 6 % ( ( 3 7 , 0 b & + > / , 1 8 $ 5 7 b & . @ 0 6 9 table 8. stm8af6226 lqfp32 pin description lqfp32 pin name type input output main function (after reset) default alternate function alternate function after remap [option bit] floating wpu ext. interrupt high sink (1) speed od pp 1 nrst i/o - x ----- reset - 2 pa1/ oscin (2) i/o x x x - o1 x x port a1 resonator/ crystal in - 3 pa2/ oscout i/o x x x - o1 x x port a2 resonator/ crystal out - pinout and pin description STM8AF6213/23/23a/26 30/106 docid025118 rev 5 4 vss s - - - - - - - digital ground - 5 vcap s - - - - - - - 1.8 v regulator capacitor - 6 vdd s - - - - - - - digital power supply - 7 pa3/ tim5_ch3 [spi_nss] [linuart_tx] i/o x x x hs o3 x x port a3 timer 52 channel 3 spi master/ slave select [afr1]/ linuart data transmit [afr1:0] 8 pf4 [linuart_rx] i/o x x - - o1 x x port f4 linuart data receive [afr1:0] - 9 pb7 i/o x x x - o1 x x port b7 - - 10 pb6 i/o x x x - o1 x x port b6 - - 11 pb5/ i2c_sda [tim1_bkin] i/o x - x-o1 t (3) - port b5 i2c data timer 1 - break input [afr4] 12 pb4/ i2c_scl [adc_etr] i/o x -x -o1t (3) - port b4 i2c clock adc external trigger [afr4] 13 pb3/ ain3/tim1_et r i/o x x x hs o3 x x port b3 analog input 3/ timer 1 external trigger - 14 pb2/ ain2/ tim1_ch3n i/o x x x hs o3 x x port b2 analog input 2/ timer 1 - inverted channel 3 - 15 pb1/ ain1/ tim1_ch2n i/o x x x hs o3 x x port b1 analog input 1/ timer 1 - inverted channel 2 - 16 pb0/ ain0/ tim1_ch1n i/o x x x hs o3 x x port b0 analog input 0/ timer 1 - inverted channel 1 - table 8. stm8af6226 lqfp32 pin description (continued) lqfp32 pin name type input output main function (after reset) default alternate function alternate function after remap [option bit] floating wpu ext. interrupt high sink (1) speed od pp docid025118 rev 5 31/106 STM8AF6213/23/23a/26 pinout and pin description 103 17 pe5/ spi_nss [tim1_ch1n] i/o x x x hs o3 x x port e5 spi master/ slave select timer 1 - inverted channel 1 [afr1:0] 18 pc1/ tim1_ch1/ linuart_ck [tim1_ch2n] i/o x x x hs o3 x x port c1 timer 1 - channel 1 linuart clock timer 1 - inverted channel 2 [afr1:0] 19 pc2/ tim1_ch2 [tim1_ch3n] i/o x x x hs o3 x x port c2 timer 1 - channel 2 timer 1 - inverted channel 3 [afr1:0] 20 pc3/ tim1_ch3/[tli] [tim1_ch1n] i/o x x x hs o3 x x port c3 timer 1 - channel 3 to p l e v e l interrupt [afr3] timer 1 inverted channel 1 [afr7] 21 pc4/ tim1_ch4/ clk_cco/[ain 2][tim1_ch2n] i/o x x x hs o3 x x port c4 timer 1 - channel 4 /configurable clock output analog input 2 [afr2]timer 1 inverted channel 2 [afr7] 22 pc5/spi_sck [tim5_ch1] i/o x x x hs o3 x x port c5 spi clock timer 5 channel 1 [afr0] 23 pc6/ spi_mosi [tim1_ch1] i/o x x x hs o3 x x port c6 pi master out/slave in timer 1 channel 1 [afr0] 24 pc7/ spi_miso [tim1_ch2] i/o x x x hs o3 x x port c7 spi master in/ slave out timer 1 channel 2[afr0] 25 pd0/ tim1_bkin [clk_cco] i/o x x x hs o3 x x port d0 timer 1 - break input configurable clock output [afr5] 26 pd1/ swim (4) i/o x x x hs o4 x x port d1 swim data interface - table 8. stm8af6226 lqfp32 pin description (continued) lqfp32 pin name type input output main function (after reset) default alternate function alternate function after remap [option bit] floating wpu ext. interrupt high sink (1) speed od pp pinout and pin description STM8AF6213/23/23a/26 32/106 docid025118 rev 5 27 pd2/[ain3] [tim5_ch3] i/o x x x hs o3 x x port d2 - analog input 3 [afr2] timer 52 - channel 3 [afr1] 28 pd3/ ain4/ tim5_ch2/ adc_etr i/o x x x hs o3 x x port d3 analog input 4 timer 52 - channel 2/adc external trigger - 29 pd4/ tim5_ch1/ beep [linuart_ck] i/o x x x hs o3 x x port d4 timer 5 - channel 1/beep output linuart clock [afr2] 30 pd5/ ain5/ linuart_tx i/o x x x hs o3 x x port d5 analog input 5/ linuart data transmit - 31 pd6/ ain6/ linuart_rx i/o x x x hs o3 x x port d6 analog input 6/ linuart data receive - 32 pd7/ tli [tim1_ch4] i/o x x x hs o3 x x port d7 to p l e v e l interrupt timer 1 - channel 4 [afr6] 1. i/o pins used simultaneously for high current source/sink must be uniform ly spaced around the package. in addition, the total driven current must respect the absolute maximum ratings (see section: absolute maximum ratings ). 2. when the mcu is in halt/active-halt m ode, pa1 is automatically configured in input weak pull-up and cannot be used for waking up the device. in this mode, the output state of pa1 is not driven. it is recommended to use pa1 only in input mode if halt/active-halt is used in the application. 3. in the open-drain output column, ?t? defines a true open-drain i/o (p-buffer, weak pull-up, and protection diode to vdd are not implemented). 4. the pd1 pin is in input pull-up during the reset phase and after internal reset release. table 8. stm8af6226 lqfp32 pin description (continued) lqfp32 pin name type input output main function (after reset) default alternate function alternate function after remap [option bit] floating wpu ext. interrupt high sink (1) speed od pp docid025118 rev 5 33/106 STM8AF6213/23/23a/26 pinout and pin description 103 5.3 alternate func tion remapping as shown in the rightmost column of table 6 , table 7 and table 8 some alternate functions can be remapped at different i/o ports by programming one of eight afr (alternate function remap) option bits. refer to section 8: option bytes on page 47 . when the remapping option is active, the default alternat e function is no longer available. to use an alternate function, the corresponding peripheral must be enabled in the peripheral registers. alternate function remapping does not effect gpio capabilities of the i/o ports (see the gpio section of stm8s series and stm8af se ries 8-bit microcontrollers reference manual, rm0016). memory and register map STM8AF6213/23/23a/26 34/106 docid025118 rev 5 6 memory and register map 6.1 memory map figure 6. memory map ) o d v k s u r j u d p p h p r u \ . e \ w h [ 5 $ 0 . e \ w h e \ w h v w d f n [ ) e \ w h g d w d ( ( 3 5 2 0 5 h v h u y h g 5 h v h u y h g [ ) ) ) l q w h u u x s w y h f w r u v [ ) ) ) [ [ & 3 8 6 : , 0 g h e x j , 7 & u h j l v w h u v [ ) 5 h v h u y h g 5 h v h u y h g 2 s w l r q e \ w h v [ $ [ [ [ 5 h v h u y h g 8 q l t x h , ' [ [ * 3 , 2 d q g s h u l s k h u d o u h j l v w h u v 0 6 9 5 h v h u y h g [ $ [ ) ) ) [ ) [ ) ) ) [ ( ) ) [ ) ) [ [ [ [ % [ ) ) [ [ ) ) ) [ [ ) ) docid025118 rev 5 35/106 STM8AF6213/23/23a/26 memory and register map 103 6.2 register map 6.2.1 i/o port hardware register map table 9. memory model for the devices covered in this datasheet flash program memory size flash program memory end address ram size ram end address stack roll-over address 8 k 0x00 9fff 1 k 0x00 03ff 0x00 0200 4 k 0x00 8fff table 10. i/o port hardware register map address block register label register name reset status 0x00 5000 port a pa_odr port a data output latch register 0x00 0x00 5001 pa_idr port a input pin value register 0xxx (1) 0x00 5002 pa_ddr port a data direction register 0x00 0x00 5003 pa_cr1 port a control register 1 0x00 0x00 5004 pa_cr2 port a control register 2 0x00 0x00 5005 port b pb_odr port b data output latch register 0x00 0x00 5006 pb_idr port b input pin value register 0xxx (1) 0x00 5007 pb_ddr port b data direction register 0x00 0x00 5008 pb_cr1 port b control register 1 0x00 0x00 5009 pb_cr2 port b control register 2 0x00 0x00 500a port c pc_odr port c data output latch register 0x00 0x00 500b pb_idr port c input pin value register 0xxx (1) 0x00 500c pc_ddr port c data direction register 0x00 0x00 500d pc_cr1 port c control register 1 0x00 0x00 500e pc_cr2 port c control register 2 0x00 0x00 500f port d pd_odr port d data output latch register 0x00 0x00 5010 pd_idr port d input pin value register 0xxx (1) 0x00 5011 pd_ddr port d data direction register 0x00 0x00 5012 pd_cr1 port d control register 1 0x02 0x00 5013 pd_cr2 port d control register 2 0x00 memory and register map STM8AF6213/23/23a/26 36/106 docid025118 rev 5 0x00 5014 port e pe_odr port e data output latch register 0x00 0x00 5015 pe_idr port e input pin value register 0xxx (1) 0x00 5016 pe_ddr port e data direction register 0x00 0x00 5017 pe_cr1 port e control register 1 0x00 0x00 5018 pe_cr2 port e control register 2 0x00 0x00 5019 port f pf_odr port f data output latch register 0x00 0x00 501a pf_idr port f input pin value register 0xxx (1) 0x00 501b pf_ddr port f data direction register 0x00 0x00 501c pf_cr1 port f control register 1 0x00 0x00 501d pf_cr2 port f control register 2 0x00 1. depends on the external circuitry. table 11. general hardware register map address block register label register name reset status 0x00 501e to 0x00 5069 reserved area (60 byte) 0x00 505a flash flash_cr1 flash control register 1 0x00 0x00 505b flash_cr2 flash control register 2 0x00 0x00 505c flash_ncr2 flash complementary control register 2 0xff 0x00 505d flash_fpr flash protection register 0x00 0x00 505e flash_nfpr flash complementary protection register 0xff 0x00 505f flash_iapsr flash in-application programming status register 0x40 0x00 5060 to 0x00 5061 reserved area (2 byte) 0x00 5062 flash flash_pukr flash program memory unprotection register 0x00 0x00 5063 reserved area (1 byte) 0x00 5064 flash flash_dukr data eepr om unprotection register 0x00 0x00 5065 to 0x00 509f reserved area (59 byte) 0x00 50a0 itc exti_cr1 external interrupt control register 1 0x00 0x00 50a1 exti_cr2 external interrupt control register 2 0x00 0x00 50a2 to 0x00 50b2 reserved area (17 byte) table 10. i/o port hardware register map (continued) address block register label register name reset status docid025118 rev 5 37/106 STM8AF6213/23/23a/26 memory and register map 103 0x00 50b3 rst rst_sr reset status register 0xxx (1) 0x00 50b4 to 0x00 50bf reserved area (12 byte) 0x00 50c0 clk clk_ickr internal clock control register 0x01 0x00 50c1 clk_eckr external clock control register 0x00 0x00 50c2 reserved area (1 byte) 0x00 50c3 clk clk_cmsr clock master status register 0xe1 0x00 50c4 clk_swr clock mast er switch register 0xe1 0x00 50c5 clk_swcr clock switch control register 0xxx 0x00 50c6 clk_ckdivr clock divider register 0x18 0x00 50c7 clk_pckenr1 peripheral clock gating register 1 0xff 0x00 50c8 clk_cssr clock secu rity system register 0x00 0x00 50c9 clk_ccor configurable clock control register 0x00 0x00 50ca clk_pckenr2 peripheral clock gating register 2 0xff 0x00 50cb reserved area (1 byte) 0x00 50cc clk clk_hsitrimr hsi clock calibration trimming register 0x00 0x00 50cd clk_swimccr swim clock control register 0bxxxx xxx0 0x00 50ce to 0x00 50d0 reserved area (3 byte) 0x00 50d1 wwdg wwdg_cr wwdg control register 0x7f 0x00 50d2 wwdg_wr wwdr window register 0x7f 0x00 50d3 to 0x00 50df reserved area (13 byte) 0x00 50e0 iwdg iwdg_kr iwdg key register 0xxx (2) 0x00 50e1 iwdg_pr iwdg prescaler register 0x00 0x00 50e2 iwdg_rlr iwdg reload register 0xff 0x00 50e3 to 0x00 50ef reserved area (13 byte) 0x00 50f0 awu awu_csr1 awu control/status register 1 0x00 0x00 50f1 awu_apr awu asynchronous prescaler buffer register 0x3f 0x00 50f2 awu_tbr awu timebase selection register 0x00 0x00 50f3 beep beep_csr beep contro l/status register 0x1f 0x00 50f4 to 0x00 50ff reserved area (12 byte) table 11. general hardware register map (continued) address block register label register name reset status memory and register map STM8AF6213/23/23a/26 38/106 docid025118 rev 5 0x00 5200 spi spi_cr1 spi control register 1 0x00 0x00 5201 spi_cr2 spi control register 2 0x00 0x00 5202 spi_icr spi interrupt control register 0x00 0x00 5203 spi_sr spi stat us register 0x02 0x00 5204 spi_dr spi data register 0x00 0x00 5205 spi_crcpr spi crc polynomial register 0x07 0x00 5206 spi_rxcrcr spi rx crc register 0xff 0x00 5207 spi_txcrcr spi tx crc register 0xff 0x00 5208 to 0x00 520f reserved area (8 byte) 0x00 5210 i2c i2c_cr1 i2c control register 1 0x00 0x00 5211 i2c_cr2 i2c control register 2 0x00 0x00 5212 i2c_freqr i2c frequency register 0x00 0x00 5213 i2c_oarl i2c own address register low 0x00 0x00 5214 i2c_oarh i2c own address register high 0x00 0x00 5215 reserved area (1 byte) 0x00 5216 i2c_dr i2c data register 0x00 0x00 5217 i2c_sr1 i2c status register 1 0x00 0x00 5218 i2c_sr2 i2c status register 2 0x00 0x00 5219 i2c_sr3 i2c status register 3 0x00 0x00 521a i2c_itr i2c interrupt control register 0x00 0x00 521b i2c_ccrl i2c clock control register low 0x00 0x00 521c i2c_ccrh i2c clock control register high 0x00 0x00 521d i2c_triser i2c trise register 0x02 0x00 521e i2c_pecr i2c packet error checking register 0x00 0x00 521f to 0x00 522f reserved area (17 byte) table 11. general hardware register map (continued) address block register label register name reset status docid025118 rev 5 39/106 STM8AF6213/23/23a/26 memory and register map 103 0x00 5230 linuart uart4_sr linuart status register 0xc0 0x00 5231 uart4_dr linuart data register 0xxx 0x00 5232 uart4_brr1 linuart baud rate register 1 0x00 0x00 5233 uart4_brr2 linuart baud rate register 2 0x00 0x00 5234 uart4_cr1 linuart control register 1 0x00 0x00 5235 uart4_cr2 linuart control register 2 0x00 0x00 5236 uart4_cr3 linuart control register 3 0x00 0x00 5237 uart4_cr4 linuart control register 4 0x00 0x00 5238 reserved 0x00 5239 uart4_cr6 linuart control register 6 0x00 0x00 523a uart4_gtr linuart guard time register 0x00 0x00 523b uart4_pscr linuart prescaler 0x00 0x00 523c to 0x00 523f reserved area (20 byte) table 11. general hardware register map (continued) address block register label register name reset status memory and register map STM8AF6213/23/23a/26 40/106 docid025118 rev 5 0x00 5250 tim1 tim1_cr1 tim1 control register 1 0x00 0x00 5251 tim1_cr2 tim1 control register 2 0x00 0x00 5252 tim1_smcr tim1 slave mode control register 0x00 0x00 5253 tim1_etr tim1 external trigger register 0x00 0x00 5254 tim1_ier tim1 interrupt enable register 0x00 0x00 5255 tim1_sr1 tim1 status register 1 0x00 0x00 5256 tim1_sr2 tim1 status register 2 0x00 0x00 5257 tim1_egr tim1 even t generation register 0x00 0x00 5258 tim1_ccmr1 tim1 capture/ compare mode register 1 0x00 0x00 5259 tim1_ccmr2 tim1 capture/ compare mode register 2 0x00 0x00 525a tim1_ccmr3 tim1 captur e/compare mode register 3 0x00 0x00 525b tim1_ccmr4 tim1 captur e/compare mode register 4 0x00 0x00 525c tim1_ccer1 tim1 captur e/compare enable register 1 0x00 0x00 525d tim1_ccer2 tim1 captur e/compare enable register 2 0x00 0x00 525e tim1_cntrh tim1 counter high 0x00 0x00 525f tim1_cntrl tim1 counter low 0x00 0x00 5260 tim1_pscrh tim1 prescaler register high 0x00 0x00 5261 tim1_pscrl tim1 prescaler register low 0x00 0x00 5262 tim1_arrh tim1 auto-reload register high 0xff 0x00 5263 tim1_arrl tim1 auto-reload register low 0xff 0x00 5264 tim1_rcr tim1 repetit ion counter register 0x00 0x00 5265 tim1_ccr1h tim1 capture/ compare register 1 high 0x00 0x00 5266 tim1_ccr1l tim1 capture/ compare register 1 low 0x00 0x00 5267 tim1_ccr2h tim1 capture/ compare register 2 high 0x00 0x00 5268 tim1_ccr2l tim1 capture/ compare register 2 low 0x00 0x00 5269 tim1_ccr3h tim1 capture/ compare register 3 high 0x00 0x00 526a tim1_ccr3l tim1 captur e/compare register 3 low 0x00 0x00 526b tim1_ccr4h tim1 capture/ compare register 4 high 0x00 0x00 526c tim1_ccr4l tim1 captur e/compare register 4 low 0x00 0x00 526d tim1_bkr tim1 break register 0x00 0x00 526e tim1_dtr tim1 dead-time register 0x00 0x00 526f tim1_oisr tim1 output idle state register 0x00 0x00 5270 to 0x00 52ff reserved area (147 byte) table 11. general hardware register map (continued) address block register label register name reset status docid025118 rev 5 41/106 STM8AF6213/23/23a/26 memory and register map 103 0x00 5300 tim5 tim5_cr1 tim5 control register 1 0x00 0x00 5301 tim5_cr2 tim5 control register 2 0x00 0x00 5302 tim5_smcr tim5 slave mode control register 0x00 0x00 5303 tim5_ier tim5 interrupt enable register 0x00 0x00 5304 tim5_sr1 tim5 status register 1 0x00 0x00 5305 tim5_sr2 tim5 status register 2 0x00 0x00 5306 tim5_egr tim5 even t generation register 0x00 0x00 5307 tim5_ccmr1 tim5 captur e/compare mode register 1 0x00 0x00 5308 tim5_ccmr2 tim5 captur e/compare mode register 2 0x00 0x00 5309 tim5_ccmr3 tim5 captur e/compare mode register 3 0x00 0x00 530a tim5_ccer1 tim5 captur e/compare enable register 1 0x00 0x00 530b tim5_ccer2 tim5 captur e/compare enable register 2 0x00 00 530c0x tim5_cntrh tim5 counter high 0x00 0x00 530d tim5_cntrl tim5 counter low 0x00 0x00 530e tim5_pscr tim5 prescaler register 0x00 0x00 530f tim5_arrh tim5 auto-reload register high 0xff 0x00 5310 tim5_arrl tim5 auto-reload register low 0xff 0x00 5311 tim5_ccr1h tim5 captur e/compare register 1 high 0x00 0x00 5312 tim5_ccr1l tim5 capture/ compare register 1 low 0x00 0x00 5313 tim5_ccr2h tim5 capture/compare reg. 2 high 0x00 0x00 5314 tim5_ccr2l tim5 capture/ compare register 2 low 0x00 0x00 5315 tim5_ccr3h tim5 capture/co mpare register 3 high 0x00 0x00 5316 tim5_ccr3l tim5 capture/ compare register 3 low 0x00 0x00 5317 to 0x00 533f reserved area (43 byte) 0x00 5340 tim6 tim6_cr1 tim6 control register 1 0x00 0x00 5341 tim6_cr2 tim6 control register 2 0x00 0x00 5342 tim6_smcr tim6 slave mode control register 0x00 0x00 5343 tim6_ier tim6 interrupt enable register 0x00 0x00 5344 tim6_sr tim6 status register 0x00 0x00 5345 tim6_egr tim6 event generation register 0x00 0x00 5346 tim6_cntr tim6 counter 0x00 0x00 5347 tim6_pscr tim6 prescaler register 0x00 0x00 5348 tim6_arr tim6 auto-reload register 0xff table 11. general hardware register map (continued) address block register label register name reset status memory and register map STM8AF6213/23/23a/26 42/106 docid025118 rev 5 0x00 5349 to 0x00 53df reserved area (153 byte) 0x00 53e0 to 0x00 53f3 adc1 adc _dbxr adc data buffer registers 0x00 0x00 53f4 to 0x00 53ff reserved area (12 byte) 0x00 5400 adc1 adc _csr adc control/status register 0x00 0x00 5401 adc_cr1 adc configuration register 1 0x00 0x00 5402 adc_cr2 adc configuration register 2 0x00 0x00 5403 adc_cr3 adc configuration register 3 0x00 0x00 5404 adc_drh adc data register high 0xxx 0x00 5405 adc_drl adc data register low 0xxx 0x00 5406 adc_tdrh adc schmitt trigger disable register high 0x00 0x00 5407 adc_tdrl adc schmitt trig ger disable register low 0x00 0x00 5408 adc _htrh adc high threshold register high 0xff 0x00 5409 adc_htrl adc high threshold register low 0x03 0x00 540a adc _ltrh adc low threshold register high 0x00 0x00 540b adc_ltrl adc low threshold register low 0x00 0x00 540c adc _awsrh adc watchdog status register high 0x00 0x00 540d adc_awsrl adc watchdog status register low 0x00 0x00 540e adc _awcrh adc watchdog control register high 0x00 0x00 540f adc _awcrl adc watchdog control register low 0x00 0x00 5410 to 0x00 57ff reserved area (1008 byte) 1. depends on the previous reset source. 2. write only register. table 11. general hardware register map (continued) address block register label register name reset status docid025118 rev 5 43/106 STM8AF6213/23/23a/26 memory and register map 103 6.2.2 cpu/swim/debug module/in terrupt controller registers table 12. cpu/swim/debug module/interrupt controller registers address block register label register name reset status 0x00 7f00 cpu (1) a accumulator 0x00 0x00 7f01 pce program counter extended 0x00 0x00 7f02 pch program counter high 0x00 0x00 7f03 pcl program counter low 0x00 0x00 7f04 xh x index register high 0x00 0x00 7f05 xl x index register low 0x00 0x00 7f06 yh y index register high 0x00 0x00 7f07 yl y index register low 0x00 0x00 7f08 sph stack pointer high 0x03 0x00 7f09 spl stack pointer low 0xff 0x00 7f0a ccr condition code register 0x28 0x00 7f0b to 0x00 7f5f reserved area (85 byte) 0x00 7f60 cpu cfg_gcr global configuration register 0x00 0x00 7f70 itc itc_spr1 interrupt software priority register 1 0xff 0x00 7f71 itc_spr2 interrupt software priority register 2 0xff 0x00 7f72 itc_spr3 interrupt software priority register 3 0xff 0x00 7f73 itc_spr4 interrupt software priority register 4 0xff 0x00 7f74 itc_spr5 interrupt software priority register 5 0xff 0x00 7f75 itc_spr6 interrupt software priority register 6 0xff 0x00 7f76 itc_spr7 interrupt software priority register 7 0xff 0x00 7f77 itc_spr8 interrupt software priority register 8 0xff 0x00 7f78 to 0x00 7f79 reserved area (2 byte) 0x00 7f80 swim swim_csr swim control status register 0x00 0x00 7f81 to 0x00 7f8f reserved area (15 byte) memory and register map STM8AF6213/23/23a/26 44/106 docid025118 rev 5 0x00 7f90 dm dm_bk1re dm breakpoint 1 register extended byte 0xff 0x00 7f91 dm_bk1rh dm breakpoint 1 register high byte 0xff 0x00 7f92 dm_bk1rl dm breakpoint 1 register low byte 0xff 0x00 7f93 dm_bk2re dm breakpoint 2 register extended byte 0xff 0x00 7f94 dm_bk2rh dm breakpoint 2 register high byte 0xff 0x00 7f95 dm_bk2rl dm breakpoint 2 register low byte 0xff 0x00 7f96 dm_cr1 dm debug module control register 1 0x00 0x00 7f97 dm_cr2 dm debug module control register 2 0x00 0x00 7f98 dm_csr1 dm debug module control/status register 1 0x10 0x00 7f99 dm_csr2 dm debug module control/status register 2 0x00 0x00 7f9a dm_enfctr dm enable function register 0xff 0x00 7f9b to 0x00 7f9f reserved area (5 byte) 1. accessible by debug module only table 12. cpu/swim/debug module/interrupt controller registers (continued) address block register label register name reset status docid025118 rev 5 45/106 STM8AF6213/23/23a/26 interrupt vector mapping 103 7 interrupt vector mapping table 13. interrupt mapping priority source block description wakeup from halt mode wakeup from active-halt mode interrupt vector address ? reset reset yes yes 0x00 8000 ? trap software interrupt - - 0x00 8004 0 tli external top level interrupt - - 0x00 8008 1 awu auto-wakeup from halt - yes 0x00 800c 2 clock controller clock controller - - 0x00 8010 3 exti0 port a external interrupts yes (1) yes (1) 0x00 8014 4 exti1 port b external interrupts yes yes 0x00 8018 5 exti2 port c external interrupts yes yes 0x00 801c 6 exti3 port d external interrupts yes yes 0x00 8020 7 exti4 port e external interrupts yes yes 0x00 8024 8 exti5 port f - - 0x00 8028 9 reserved - - - 0x00 802c 10 spi end of transfer yes yes 0x00 8030 11 tim1 tim1 update/overflow/ ? underflow/trigger/break - - 0x00 8034 12 tim1 tim1 capture/compare - - 0x00 8038 13 tim5 tim5 update/overflow/trigger - - 0x00 803c 14 tim5 tim5 capture/compare - - 0x00 8040 15 reserved - - - 0x00 8044 16 reserved - - - 0x00 8048 17 linuart tx complete - - 0x00 804c 18 linuart receive register data full - - 0x00 8050 19 i 2 c i 2 c interrupts yes yes 0x00 8054 20 reserved - - - 0x00 8058 21 reserved - - - 0x00 805c 22 adc1 adc1 end of conversion/analog watchdog interrupt - - 0x00 8060 interrupt vector mapping STM8AF6213/23/23a/26 46/106 docid025118 rev 5 23 tim6 tim6 update/overflow/trigger - - 0x00 8064 24 flash eop/wr_pg_dis - - 0x00 8068 1. except pa1. table 13. interrupt mapping (continued) priority source block description wakeup from halt mode wakeup from active-halt mode interrupt vector address docid025118 rev 5 47/106 STM8AF6213/23/23a/26 option bytes 103 8 option bytes option bytes contain configurations for device hardware features as well as the memory protection of the device. except for the rop (r ead-out protection) byte, each option byte has to be stored twice, in a regular form (optx) and a complemented one (noptx) for redundancy. option bytes can be modified in icp mode (via swim) by access ing the eeprom address shown in table 14: option bytes below. option bytes can also be modified ?on the fly? by the application in iap mode, except the rop and ubc options that can only be modified in icp mode (via swim). refer to the stm8 flash programming manual (pm0051) and stm8 swim communication protocol and debug module user manual (um0470) for information on swim programming procedures. table 14. option bytes addr. option name option byte no. option bits factory default setting 765 4 3 2 1 0 0x00 4800 read-out protection (rop) opt0 rop[7:0] 0x00 0x00 4801 user boot code (ubc) opt1 ubc[7:0] 0x00 0x00 4802 nopt1 nubc[7:0] 0xff 0x00 4803 alternate function remapping (afr) opt2 afr7 afr6 afr5 afr4 afr3 afr2 afr1 afr0 0x00 0x00 4804 nopt2 nafr7 nafr6 nafr 5 nafr 4 nafr 3 nafr 2 nafr 1 nafr 0 0xff 0x00 4805 miscell. option opt3 reserved hsi trim lsi _en iwdg _hw wwdg _hw wwdg _halt 0x00 0x00 4806 nopt3 reserved nhsi trim nlsi _en niwdg _hw nwwdg _hw nwwg _halt 0xff 0x00 4807 clock option opt4 reserved ext clk ckawu sel prs c1 prs c0 0x00 0x00 4808 nopt4 reserved next clk nckawu sel nprs c1 nprs c0 0xff 0x00 4809 hse clock startup opt5 hsecnt[7:0] 0x00 0x00 480a nopt5 nhsecnt[7:0] 0xff option bytes STM8AF6213/23/23a/26 48/106 docid025118 rev 5 8.1 option byte description table 15. option byte description option byte no. description opt0 rop[7:0]: memory readout protection (rop) 0xaa: enable readout protection (w rite access via swim protocol) ? note: refer to stm8s series and stm8 af series 8-bit microcontrollers reference manual (rm0016) se ction on flash/eeprom memory readout protection for details. opt1 ubc[7:0]: user boot code area 0x00: no ubc, no write-protection ? 0x01: page 0 defined as ubc, memory write-protected ? 0x02: page 0 to 1 defined as ubc, memory write-protected ? pages 0 and 1 contain the interrupt vectors. ? ... 0x7f: pages 0 to 126 defined as ubc, memory write-protected ? other values: page 0 to 127 defined as ubc, memory write-protected. note: refer to stm8s series and stm8 af series 8-bit microcontrollers reference manual (rm0016) sectio n on flash/eeprom write protection for more details. opt2 afr[7:0] refer to the following sections for the alternate function remapping descriptions of bits [7:2] and [1:0] respectively. opt3 hsitrim: high-speed internal clock trimming register size 0: 3-bit trimming supported in clk_hsitrimr register 1: 4-bit trimming supported in clk_hsitrimr register lsi_en: low-speed internal clock enable 0: lsi clock is not available as cpu clock source 1: lsi clock is available as cpu clock source iwdg_hw: independent watchdog 0: iwdg independent watchdog activated by software 1: iwdg independent watchdog activated by hardware wwdg_hw: window watchdog activation 0: wwdg window watchdog activated by software 1: wwdg window watchdog activated by hardware wwdg_halt: window watchdog reset on halt 0: no reset generated on halt if wwdg active 1: reset generated on halt if wwdg active docid025118 rev 5 49/106 STM8AF6213/23/23a/26 option bytes 103 8.2 STM8AF6213/23/23a/26 altern ate function remapping bits opt4 extclk: external clock selection 0: external crystal connected to oscin/oscout 1: external clock signal on oscin ckawusel: auto-wakeup unit/clock 0: lsi clock source selected for awu 1: hse clock with prescaler sele cted as clock source for awu prsc[1:0]: awu clock prescaler 0x: 16 mhz to 1 28 khz prescaler ? 10: 8 mhz to 128 khz prescaler ? 11: 4 mhz to 128 khz prescaler opt5 hsecnt[7:0]: hse crystal oscillator stabilization time 0x00: 2048 hse cycles 0xb4: 128 hse cycles 0xd2: 8 hse cycles 0xe1: 0.5 hse cycles table 15. option byte description (continued) option byte no. description table 16. stm8af6226 alternate function remapping bits [7:2] for 32-pin packages option byte number description (1) 1. do not use more than one remapping option in the same port. opt2 afr7: alternate function remapping option 7 0: afr7 remapping option inactive: default alternate function (2) ? 1: port c3 alternate f unction = = tim1_ch1n; ? port c4 alternate function = tim1_ch2n afr6: alternate function remapping option 6 0: afr6 remapping option inactive: default alternate function (2) ? 1: port d7 alternate function = tim1_ch4. afr5: alternate function remapping option 5 0: afr5 remapping option inactive: default alternate function (2) . ? 1: port d0 alternate function = clk_cco. afr4: alternate function remapping option 4 0: afr4 remapping option inactive: default alternate function (2) . ? 1: port b4 alternate function = a dc_etr; port b5 alternate function = tim1_bkin. afr3: alternate function remapping option 3 0: afr3 remapping option inactive: default alternate function (2) ? 1: port c3 alternate function = tli afr2: alternate function remapping option 2 0: afr2 remapping option inactive: default alternate function (2) ? 1: port c4 alternate function = ain2 ; port d2 alternate function = ain3; port d4 alternate function = linuart_ck 2. refer to the pin description. option bytes STM8AF6213/23/23a/26 50/106 docid025118 rev 5 table 17. STM8AF6213 and stm8af6223 alternate function remapping bits [7:2] for 20-pin packages option byte number description (1) 1. do not use more than one remapping option in the same port. opt2 afr7: alternate function remapping option 7 0: afr7 remapping option inactive: default alternate function (2) ? 1: port c3 alternate f unction = = tim1_ch1n; ? port c4 alternate function = tim1_ch2n afr6: alternate function remapping option 6 reserved afr5: alternate function remapping option 5 reserved afr4: alternate function remapping option 4 0: afr4 remapping option inactive: default alternate function (2) . ? 1: port b4 alternate function = a dc_etr; port b5 alternate function = tim1_bkin. afr3: alternate function remapping option 3 0: afr3 remapping option inactive: default alternate function (2) ? 1: port c3 alternate function = tli afr2: alternate function remapping option 2 0: afr2 remapping option inactive: default alternate function (2) ? 1: port d4 alternate function = linuart_ck 2. refer to the pin description. table 18. stm8af6223a alternate function remapping bits [7:2] for 20-pin packages option byte number description (1) 1. do not use more than one remapping option in the same port. opt2 afr7: alternate function remapping option 7 0: afr7 remapping option inactive: default alternate function (2) ? 1: port c4 alternate function = tim1_ch2n afr6: alternate function remapping option 6 reserved afr5: alternate function remapping option 5 reserved afr4: alternate function remapping option 4 0: afr4 remapping option inactive: default alternate function (2) . ? 1: port b4 alternate function = a dc_etr; port b5 alternate function = tim1_bkin. afr3: alternate function remapping option 3 reserved. afr2: alternate function remapping option 2 0: afr2 remapping option inactive: default alternate function (2) ? 1: port d4 alternate function = linuart_ck 2. refer to the pin description. docid025118 rev 5 51/106 STM8AF6213/23/23a/26 option bytes 103 table 19. stm8af6226 alternate function remapping bits [1:0] for 32-pin packages afr1 option bit value afr0 option bit value i/o port alternate function mapping 0 0 afr1 and afr0 remapping options inactive: default alternate functions (1) 1. refer to the pin descriptions. 0 1 pc5 tim5_ch1 pc6 tim1_ch1 pc7 tim1_ch2 1 0 pa3 spi_nss pd2 tim5_ch3 1 (2) 2. if both afr1 and afr0 option bits are set, the spi hardware nss management feature is no more available. if this remapping option is selected and the spi is enabled, the ssm bit must be configured in the spi_cr2 register to select software nss management. 1 (2) pd2 tim5_ch3 pc5 tim5_ch1 pc6 tim1_ch1 pc7 tim1_ch2 pc2 tim1_ch3n pc1 tim1_ch2n pe5 tim1_ch1n pa3 linuart_tx pf4 linuart_rx table 20. STM8AF6213/stm8af6223 altern ate function remapping bits [1:0] for 20-pin packages afr1 option bit value afr0 option bit value i/o port alternate function mapping 0 0 afr1 and afr0 remapping options inactive: default alternate functions (1) 0 1 pc5 tim5_ch1 pc6 tim1_ch1 pc7 tim1_ch2 1 0 pa3 spi_nss pd2 tim5_ch3 option bytes STM8AF6213/23/23a/26 52/106 docid025118 rev 5 1 1 pd2 tim5_ch3 pc5 tim5_ch1 pc6 tim1_ch1 pc7 tim1_ch2 pc2 not available pc1 not available pe5 not available pa3 spi_nss pf4 not available 1. refer to the pin descriptions. table 21. stm8af6223a alternate function remapping bits [1:0] for 20-pin packages afr1 option bit value afr0 option bit value i/o port alternate function mapping 00 afr1 and afr0 remapping options inactive: default alternate functions (1) 01 pc5 tim5_ch1 pc6 tim1_ch1 pc7 tim1_ch2 1 0 pa3 not available pd2 tim5_ch3 1 (2) 1 (2) pd2 tim5_ch3 pc5 tim5_ch1 pc6 tim1_ch1 pc7 tim1_ch2 pc2 not available pc1 not available pe5 not available pa3 not available pf4 not available 1. refer to the pin descriptions. 2. if both afr1 and afr0 option bits are set, the spi hardware nss management feature is no more available. if this remapping option is selected and the spi is enabled, the ssm bit must be configured in the spi_cr2 register to select software nss management. table 20. STM8AF6213/stm8af6223 altern ate function remapping bits [1:0] for 20-pin packages (continued) afr1 option bit value afr0 option bit value i/o port alternate function mapping docid025118 rev 5 53/106 STM8AF6213/23/23a/26 electrical characteristics 103 9 electrical characteristics 9.1 parameter conditions unless otherwise specified, all voltages are referred to v ss . 9.1.1 minimum and maximum values unless otherwise specified the minimum and ma ximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at t a = -40 c, t a = 25 c, and ? t a = t amax (given by the selected temperature range). data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. 9.1.2 typical values unless otherwise specified, typical data are based on t a = 25 c, v dd = 5.0 v. they are given only as design guidelines and are not tested. typical adc accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range . 9.1.3 typical curves unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 9.1.4 loading capacitor the loading conditions used for pin parameter measurement are shown in figure 7 . figure 7. pin loading conditions 6 7 0 $ 3 , 1 s ) 0 6 y 9 electrical characteristics STM8AF6213/23/23a/26 54/106 docid025118 rev 5 9.1.5 pin input voltage the input voltage measurement on a pin of the device is described in figure 8 . figure 8. pin input voltage 9.2 absolute maximum ratings stresses above those listed as ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device under these conditions is not implied. ex posure to maximum rating conditions for extended periods may affect device reliability. 6 7 0 $ 3 , 1 0 6 y 9 9 , 1 table 22. voltage characteristics symbol ratings min max unit v ddx - v ss supply voltage (including v dda and v ddio ) (1) 1. all power (v dd ) and ground (v ss ) pins must always be connected to the external power supply -0.3 6.5 v v in input voltage on true open drain pins (2) 2. i inj(pin) must never be exceeded. this is implicitly insured if v in maximum is respected. if v in maximum cannot be respected, the injection current must be limited externally to the i inj(pin) value. a positive injection is induced by v in > v dd while a negative injection is induced by v in < v ss . for true open-drain pads, there is no positive injection current, and the corresponding v in maximum must always be respected v ss - 0.3 6.5 v input voltage on any other pin (2) v ss - 0.3 v dd + 0.3 |v ddx - v dd | variations between different power pins - 50 mv |v ssx - v ss | variations between all the different ground pins - 50 v esd electrostatic discharge voltage see absolute maximum ratings (electrical sensitivity) on page 90 docid025118 rev 5 55/106 STM8AF6213/23/23a/26 electrical characteristics 103 table 23. current characteristics symbol ratings max. (1) 1. data based on characterization results, not tested in production. unit i vdd total current into v dd power lines (source) (2) 2. all power (v dd , v ddio , v dda ) and ground (v ss , v ssio , v ssa ) pins must always be connected to the external supply. 100 ma i vss total current out of v ss ground lines (sink) (2) 80 i io output current sunk by any i/o and control pin 20 output current source by any i/os and control pin -20 i inj(pin) (3) (4) 3. i inj(pin) must never be exceeded. this is implicitly insured if v in maximum is respected. if v in maximum cannot be respected, the injection current must be limited externally to the i inj(pin) value. a positive injection is induced by v in >v dd while a negative injection is induced by v in docid025118 rev 5 57/106 STM8AF6213/23/23a/26 electrical characteristics 103 figure 9. f cpumax versus v dd table 27. operating conditi ons at power-up/power-down symbol parameter conditions min typ max unit t vdd v dd rise time rate - 2 (1) 1. guaranteed by design, not tested in production - ? s/v v dd fall time rate (2) 2. reset is always generated after a t temp delay. the application must ensure that v dd is still above the minimum operating voltage (v dd min) when the t temp delay has elapsed. - 2 (1) - ? t temp reset release delay v dd rising - - 1.7 ms v it+ power-on reset threshold (3) 3. there is inrush current into v dd present after device power on to charge c ext capacitor. this inrush energy depends from c ext capacitor value. for example, a c ext of 1 f requires q=1 f x 1.8v = 1.8 c. - 2.6 (1) 2.7 2.85 v v it- brown-out reset threshold - 2.5 2.65 2.8 (1) v hys(bor) brown-out reset hysteresis -- 70 (1) -mv 0 6 y 9 ? ? e ) x q f w l r q d o l w \ j x d u d q w h h g # 7 $ w r ? & 6 x s s o \ y r o w d j h 9 ) x q f w l r q d o l w \ q r w j x d u d q w h h g l q w k l v d u h d i & 3 8 0 + ] electrical characteristics STM8AF6213/23/23a/26 58/106 docid025118 rev 5 9.3.1 vcap external capacitor stabilization for the main regulator is achi eved connecting an external capacitor c ext to the v cap pin. c ext is specified in table 26 . care should be taken to limit the series inductance to less than 15 nh. figure 10. external capacitor c ext 1. legend: esr is the equivalent series resist ance and esl is the equivalent inductance. 9.3.2 supply current characteristics the current consumption is measured as described in section 4.3: interrupt controller . total current consumption in run mode the mcu is placed under the following conditions: ? all i/o pins in input mode with a static value at v dd or v ss (no load) ? all peripherals are disabled (clock stopped by peripheral clock gating registers) except if explicitly mentioned. subject to general operating conditions for v dd and t a . unless otherwise specified, da ta are based on characterization results, and not tested in production. 0 6 y 9 ( 6 5 5 / h d n ( 6 / & table 28. total current consumption with code execution in run mode at v dd = 5 v symbol parameter conditions typ max unit i dd(run) supply current in run mode, code executed from ram f cpu = f master = 16 mhz hse crystal osc. (16 mhz) 2.3 - ma hse user ext. clock (16 mhz) 2 2.35 hsi rc osc. (16 mhz) 1.7 2 (1) f cpu = f master /128= 125 khz hse user ext. clock (16 mhz) 0.86 - hsi rc osc. (16 mhz) 0.7 0.87 f cpu = f master /128= 15.625 khz hsi rc osc. (16 mhz/8) 0.46 0.58 f cpu = f master = 28 khz lsi rc osc. (128 khz) 0.41 0.55 docid025118 rev 5 59/106 STM8AF6213/23/23a/26 electrical characteristics 103 i dd(run) supply current in run mode, code executed from flash f cpu = f master = 16 mhz hse crystal osc. (16 mhz) 4.5 - ma hse user ext. clock (16 mhz) 4.3 4.75 hsi rc osc. (16 mhz) 3.7 4.5 (1) supply current in run mode, code executed from flash f cpu = f master = 2 mhz hsi rc osc. (16 mhz/8) (2) 0.84 2 (1) f cpu = f master /128 = 125 khz hsi rc osc. (16 mhz) 0.72 0.9 f cpu = f master /128 = 15.625 khz hsi rc osc. (16 mhz/8) 0.46 0.58 f cpu = f master = 128 khz lsi rc osc. (128 khz) 0.42 0.57 1. tested in production. 2. default clock configuration m easured with all peripherals off. table 29. total current consumption with code execution in run mode at v dd = 3.3 v symbol parameter conditions typ max (1) unit i dd(run) supply current in run mode, code executed from ram f cpu = f master =16 mhz hse crystal osc. (16 mhz) 1.8 - ma hse user ext. clock (16 mhz) 2 2.3 hsi rc osc. (16 mhz) 1.5 2 f cpu = f master /128 = 125 khz hse user ext. clock (16 mhz) 0.81 - hsi rc osc. (16 mhz) 0.7 0.87 f cpu = f master / 128 = 15.625 khz hsi rc osc. (16 mhz/8) 0.46 0.58 f cpu = f master =128 khz lsi rc osc. (128 khz) 0.41 0.55 supply current in run mode, code executed from flash f cpu = f master = 16 mhz hse crystal osc. (16 mhz) 4 - hse user ext. clock (16 mhz) 3.9 4.7 hsi rc osc. (16 mhz) 3.7 4.5 f cpu = f master =2 mhz hsi rc osc. (16 mhz/8) (2) 0.84 1.05 f cpu = f master / 128 = 125 khz hsi rc osc. (16 mhz) 0.72 0.9 f cpu = f master /128 = 15.625 khz hsi rc osc. (16 mhz/8) 0.46 0.58 f cpu = f master =128 khz lsi rc osc. (128 khz) 0.42 0.57 1. data based on characterization results, not tested in production. 2. default clock configuration m easured with all peripherals off. table 28. total current consumption with code execution in run mode at v dd = 5 v (continued) symbol parameter conditions typ max unit electrical characteristics STM8AF6213/23/23a/26 60/106 docid025118 rev 5 total current consumption in wait mode unless otherwise specified, da ta based are on characterization results, and not tested in production. table 30. total current consumption in wait mode at v dd = 5 v symbol parameter conditions typ max unit i dd(wfi) supply current in wait mode f cpu = f master = 16 mhz hse crystal osc. (16 mhz) 1.6 - ma hse user ext. clock (16 mhz) 1.1 1.3 hsi rc osc. (16 mhz) 0.89 1.5 (1) f cpu = f master /128 = 125 khz hsi rc osc. (16 mhz) 0.7 0.88 f cpu = f master /128 = 15.625 khz hsi rc osc. (16 mhz/8) (2) 0.45 0.57 f cpu = f master = 128 khz lsi rc osc. (128 khz) 0.4 0.54 1. tested in production. 2. default clock configuration m easured with all peripherals off. table 31. total current consumption in wait mode at v dd = 3.3 v symbol parameter conditions typ max (1) unit i dd(wfi) supply current in wait mode f cpu = f master = 16 mhz hse crystal osc. (16 mhz) 1.1 - ma hse user ext. clock (16 mhz) 1.1 1.3 hsi rc osc. (16 mhz) 0.89 1.1 f cpu = f master /128 = 125 khz hsi rc osc. (16 mhz) 0.7 0.88 f cpu = f master /128 = 15.625 khz hsi rc osc. (16 mhz/8) (2) 0.45 0.57 f cpu = f master = 128 khz lsi rc osc. (128 khz) 0.4 0.54 1. data based on characterization results, not tested in production. 2. default clock configuration m easured with all peripherals off. docid025118 rev 5 61/106 STM8AF6213/23/23a/26 electrical characteristics 103 total current consumption in active halt mode table 32. total current consumption in active halt mode at v dd = 5 v symbol parameter conditions typ max at 85c max at 125c max at 150c unit main voltage regulator (mvr) (1) flash mode (2) clock source i dd(ah) supply current in active halt mode on operating mode hse crystal osc. (16 mhz) 1030 - - - a lsi rc osc. (128 khz) 200 260 300 - power-down mode hse crystal osc. (16 mhz) 970 - - - lsi rc osc. (128 khz) 150 200 230 - off operating mode lsi rc osc. (128 khz) 66 85 140 200 power-down mode lsi rc osc. (128 khz) 10 20 40 - 1. configured by the regah bit in the clk_ickr register. 2. configured by the ahalt bit in the flash_cr1 register. table 33. total current consumption in active halt mode at v dd = 3.3 v symbol parameter conditions typ max at 85c (1) max at 125c unit main voltage regulato r (mvr) (2) flash mode (3) clock source i dd(ah) supply current in active halt mode on operating mode hse crystal osc. (16 mhz) 550 - - a lsi rc osc. (128 khz) 200 260 290 power- down mode hse crystal osc. (16 mhz) 970 - - lsi rc osc. (128 khz) 150 200 230 off operating mode lsi rc osc. (128 khz) 66 80 105 power- down mode lsi rc osc. (128 khz) 10 18 35 1. data based on characterization results, not tested in production 2. configured by the regah bit in the clk_ickr register. electrical characteristics STM8AF6213/23/23a/26 62/106 docid025118 rev 5 total current consumption in halt mode low-power mode wakeup times 3. configured by the ahalt bit in the flash_cr1 register. table 34. total current consum ption in halt mode at v dd = 5 v symbol parameter conditions typ max at 85c max at 125c max at 150c unit i dd(h) supply current in halt mode flash in operating mode, hsi clock after wakeup 63 75 105 - a flash in power-down mode, hsi clock after wakeup 6.0 20 (1) 55 (1) 80 (1) 1. tested in production. table 35. total current consumption in halt mode at v dd = 3.3 v symbol parameter conditions typ max at 85c (1) max at 125c (1) unit i dd(h) supply current in halt mode flash in operating mode, hsi clock after wakeup 60 75 100 a flash in power-down mode, hsi clock after wakeup 4.5 17 30 1. data based on characterization results, not tested in production. table 36. wakeup times symbol parameter conditions typ max (1) unit t wu(wfi) wakeup time from wait mode to run mode (2) 0 to 16 mhz - see (3) s f cpu = f master = 16 mhz 0.56 - t wu(ah) wakeup time active halt mode to run mode (2) mvr voltage regulator on (4) flash in operating mode (5) hsi (after wakeup) 1 (6) 2 (6) 3 (6) - mvr voltage regulator off 48 (6) - 50 (6) - t wu(h) wakeup time from halt mode to run mode (2) flash in operating mode (5) 52 - flash in power-down mode (5) 54 - 1. data guaranteed by design, not tested in production. 2. measured from interrupt event to interrupt vector fetch. 3. t wu(wfi) = 2 x 1/f master + 67 x 1/f cpu . 4. configured by the regah bit in the clk_ickr register. 5. configured by the ahalt bit in the flash_cr1 register. 6. plus 1 lsi clock depending on synchronization. docid025118 rev 5 63/106 STM8AF6213/23/23a/26 electrical characteristics 103 total current consumption and timing in forced reset state current consumption for on-chip peripherals subject to general operating conditions for v dd and t a . hsi internal rc/f cpu = f master = 16 mhz, v dd = 5 v table 37. total current consumption and timing in forced reset state symbol parameter conditions typ max (1) 1. data guaranteed by design, not tested in production. unit i dd(r) supply current in reset state (2) 2. characterized with all i/os tied to v ss . v dd = 5 v 400 - a v dd = 3.3 v 300 - t resetbl reset pin release to vector fetch --150s table 38. peripheral current consumption symbol parameter typ unit i dd(tim1) tim1 supply current (1) 1. data based on a differential i dd measurement between reset configuration and timer counter running at 16 mhz. no ic/oc programmed (no i/o pads toggling). not tested in production. 210 a i dd(tim5) tim5 supply current (1) 130 i dd(tim6) tim6 supply current (1) 50 i dd(uart1) linuart supply current (2) 2. data based on a differential i dd measurement between the on-chip peripheral when kept under reset and not clocked and the on-chip peripheral when clocked and not kept under reset. no i/o pads toggling. not tested in production. 120 i dd(spi) spi supply current (2) 45 i dd(i2c) i2c supply current (2) 65 i dd(adc1) adc1 supply current (3) 3. data based on a differential i dd measurement between reset configuration and continuous a/d conversions. not tested in production. 1000 electrical characteristics STM8AF6213/23/23a/26 64/106 docid025118 rev 5 current consumption curves the following figures show typical current consumption measured with code executing in ram. figure 11. typ i dd(run) vs. v dd hse user external clock, f cpu = 16 mhz figure 12. typ i dd(run) vs. f cpu hse user external clock, v dd = 5 v docid025118 rev 5 65/106 STM8AF6213/23/23a/26 electrical characteristics 103 figure 13. typ i dd(run) vs. v dd hsei rc osc., f cpu = 16 mhz figure 14. typ i dd(wfi) vs. v dd hse user external clock, f cpu = 16 mhz electrical characteristics STM8AF6213/23/23a/26 66/106 docid025118 rev 5 figure 15. typ i dd(wfi) vs. f cpu hse user external clock, v dd = 5 v figure 16. typ i dd(wfi) vs. v dd hsi rc osc., f cpu = 16 mhz docid025118 rev 5 67/106 STM8AF6213/23/23a/26 electrical characteristics 103 9.3.3 external clock sources and timing characteristics hse user external clock subject to general operating conditions for v dd and t a . figure 17. hse external clock source table 39. hse user external clock characteristics symbol parameter condi tions min typ max unit f hse_ext user external clock source frequency -0-16mhz v hseh (1) 1. data based on characterization results, not tested in production. oscin input pin high level voltage - 0.7 x v dd -v dd + 0.3 v v v hsel (1) oscin input pin low level voltage -v ss - 0.3 x v dd i leak_hse oscin input leakage current v ss < v in < v dd -1 - +1 a 9 + 6 ( + 9 + 6 ( / ( [ w h u q d o f o r f n v r x u f h 2 6 & , 1 i + 6 ( 6 7 0 0 6 9 electrical characteristics STM8AF6213/23/23a/26 68/106 docid025118 rev 5 hse crystal/ceramic resonator oscillator the hse clock can be supplied with a 1 to 16 mh z crystal/ceramic resonator oscillator. all the information given in this paragraph is ba sed on characterization results with specified typical external components. in the application, the resonator and the load capacitors have to be placed as close as possible to the oscillato r pins in order to mini mize output distortion and startup stabilization time. re fer to the crystal resonator m anufacturer for more details (frequency, package , accuracy...). figure 18. hse oscilla tor circuit diagram table 40. hse oscillator characteristics symbol parameter conditions min typ max unit f hse external high-speed oscillator frequency -1-16mhz r f feedback resistor - - 220 - k ? c (1) recommended load capacitance (2) ---20pf i dd(hse) hse oscillator power consumption c = 20 pf, f osc = 16 mhz -- 6 (startup) 1.6 (stabilized) (3) ma c = 10 pf, f osc = 16 mhz -- 6 (startup) 1.2 (stabilized) (3) g m oscillator transconductance - 5 - - ma/v t su(hse) (4) startup time v dd is stabilized -1 - ms 1. c is approximately equivalent to 2 x crystal c load . 2. the oscillator selection can be optimized in terms of supply current using a high quality resonator with small rm value. refer to the crystal manufacturer for more details. 3. data based on characterization results, not tested in production. 4. t su(hse) is the startup time measured from the moment it is ena bled (by software) until a stab ilized 16 mhz oscillation is reached. the value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer. 0 6 y 9 2 6 & 2 8 7 2 6 & , 1 i + 6 ( w r f r u h & / 5 ) 6 7 0 5 h v r q d w r u & x u u h q w f r q w u r o j p 5 p & p / p 5 h v r q d w r u & / & 2 docid025118 rev 5 69/106 STM8AF6213/23/23a/26 electrical characteristics 103 hse oscillator critical g m formula the crystal characteristics have to be checked with the following formula: where g mcrit can be calculated with the crystal parameters as follows: r m : notional resistance (s ee crystal specification) ? l m : notional inductance (see crystal specification) ? c m : notional capacitance (see crystal specification) ? co: shunt capacitance (see crystal specification) ? c l1 = c l2 = c: grounded external capacitance 9.3.4 internal clock source s and timing characteristics subject to general operating conditions for v dd and t a . high speed internal rc oscillator (hsi) g m g mcrit ? g mcrit 2 ? ? hse f ? ?? 2 r m ? 2co c + ?? 2 = table 41. hsi oscillator characteristics symbol parameter condi tions min typ max unit f hsi frequency - - 16 - mhz acc hs hsi oscillator user trimming accuracy trimmed by the application for any v dd and t a conditions -1 (1) 1. depending on option byte setting (opt3 and nopt3) -1 (1) % -0.5 (1) -0.5 (1) hsi oscillator accuracy (factory calibrated) 3.0 v ? v dd ? 5.5 v, ? -40 c ?? t a ? 150 c -5 - 5 3.0 v ? v dd ? 5.5 v, ? -40 c ?? t a ? 125 c -3 (2) -3 (2) 2. these values are guaranteed for stm8af62xxixx order codes only. t su(hsi) hsi oscillator wakeup time ---2 (3) 3. guaranteed by characterizati on, not tested in production s i dd(hsi) hsi oscillator power consumption - - 170 250 (4) 4. data based on characterization results, not tested in production. a electrical characteristics STM8AF6213/23/23a/26 70/106 docid025118 rev 5 low speed internal rc oscillator (lsi) subject to general operating conditions for v dd and t a . 9.3.5 memory characteristics ram and hardware registers flash program memory/data eeprom memory general conditions: t a = - 40 to 150 c . table 42. lsi oscillator characteristics symbol parameter conditions min typ max unit f lsi frequency - 110 (1) 1. tested in production. 128 150 (1) khz t su(lsi) lsi oscillator wakeup time - - - 7 s i dd(lsi) lsi oscillator power consumption - - 5 - a table 43. ram and hardware registers symbol parameter conditions min unit v rm data retention mode (1) 1. minimum supply voltage without losing the data stored in ram (in halt mode or under reset) or in hardware registers (only in halt mode). guaranteed by design, not tested in production. halt mode (or reset) v it-max (2) 2. refer to the operating conditions for the value of v it-max v table 44. flash program memory/data eeprom memory symbol parameter conditions min typ max unit v dd operating voltage ? (all modes, execution/write/erase) f cpu is 0 to 16 mhz with 0 ws 3.0 - 5.5 v operating voltage ? (code execution) 2.6 - 5.5 t prog standard programming time (including erase) for byte/word/block ? (1 byte/4 byte/64 byte) --6.06.6 ms fast programming time for 1 block (64 byte) --3.03.3 t erase erase time for 1 block (64 byte) - - 3.0 3.3 docid025118 rev 5 71/106 STM8AF6213/23/23a/26 electrical characteristics 103 table 45. flash program memory symbol parameter condition min max unit t we temperature for writing and erasing - -40 150 c n we flash program memory endurance (erase/write cycles) (1) 1. the physical granularity of the memory is 4 by te, so cycling is performed on 4 byte even when a write/erase operation addresses a single byte. t a = 25 c 1000 - cycles t ret data retention time t a = 25 c 40 - years t a = 55 c 20 - table 46. data memory symbol parameter condition min max unit t we temperature for writing and erasing - -40 150 c n we data memory endurance (1) ? (erase/write cycles) 1. the physical granularity of the memory is 4 by te, so cycling is performed on 4 byte even when a write/erase operation addresses a single byte. t a = 25 c 300 k - cycles t a = -40c to 125 c 100 k (2) 2. more information on the relationship between data retention time and number of write/erase cycles is available in a separate technical document. - t ret data retention time t a = 25 c 40 (3) 3. retention time for 256b of data memory after up to 1000 cycles at 125 c. - years t a = 55 c 20 (2)(3) - electrical characteristics STM8AF6213/23/23a/26 72/106 docid025118 rev 5 9.3.6 i/o port pin characteristics general characteristics subject to general operating conditions for v dd and t a unless otherwise specified. all unused pins must be kept at a fixed voltage, using the output mode of the i/o for example or an external pull-up or pull-down resistor. table 47. i/o static characteristics symbol parameter conditions min typ max unit v il input low level voltage - -0.3 v - 0.3 x v dd v v ih input high level voltage 0.7 x v dd -v dd + 0.3 v v hys hysteresis (1) -700-mv r pu pull-up resistor v dd = 5 v, v in = v ss 35 55 80 k ? t r , t f rise and fall time ? (10% - 90%) fast i/os load = 50 pf --35 (2) ns standard and high sink i/os load = 50 pf --125 (2) fast i/os load = 20 pf 20 (2) standard and high sink i/os load = 20 pf 50 (2) i lkg digital input pad leakage current v ss ? ? v in ? ? v dd --1 (3) a i lkg ana analog input pad leakage current v ss ??? v in ??? v dd -40 c < t a < 125 c --250 (3) na v ss ??? v in ??? v dd -40 c < t a < 150 c --500 (3) i lkg(inj) leakage current in adjacent i/o (2) injection current 4 ma - - 1 (3) a 1. hysteresis voltage between schmitt trigger switching levels . based on characterization results, not tested in production. 2. data based on characterization results, not tested in production. 3. guaranteed by design. docid025118 rev 5 73/106 STM8AF6213/23/23a/26 electrical characteristics 103 figure 19. typical v il and v ih vs v dd @ 4 temperatures figure 20. typical pull-up resistance r pu vs v dd @ 4 temperatures electrical characteristics STM8AF6213/23/23a/26 74/106 docid025118 rev 5 figure 21. typical pull-up current i pu vs v dd @ 4 temperatures table 48. output driving current (standard ports) symbol parameter conditions min max unit v ol output low level with 8 pins sunk i io = 10 ma, ? v dd = 5 v - 2.0 v output low level with 4 pins sunk i io = 4 ma, ? v dd = 3.3 v - 1.0 (1) 1. data based on characterization results, not tested in production. v oh output high level with 8 pins sourced i io = 10 ma, ? v dd = 5 v 2.8 - output high level with 4 pins sourced i io = 4 ma, ? v dd = 3.3 v 2.1 (1) - table 49. output driving current (true open drain ports) symbol parameter conditions max unit v ol output low level with 2 pins sunk i io = 10 ma, v dd = 5 v 1.0 v i io = 10 ma, v dd = 3.3 v 1.5 (1) 1. data based on characterization results, not tested in production. i io = 20 ma, v dd = 5 v 2.0 (1) docid025118 rev 5 75/106 STM8AF6213/23/23a/26 electrical characteristics 103 figure 22. typ. v ol @ v dd = 5 v (standard ports) figure 23. typ. v ol @ v dd = 3.3 v (standard ports) table 50. output driving current (high sink ports) symbol parameter conditions min max unit v ol output low level with 8 pins sunk i io = 10 ma, v dd = 5 v - 0.8 v output low level with 4 pins sunk i io = 10 ma, v dd = 3.3 v - 1.0 (1) 1. data based on characterization results, not tested in production. i io = 20 ma, v dd = 5 v 1.5 (1) v oh output high level with 8 pins sourced i io = 10 ma, v dd = 5 v 4.0 - output high level with 4 pins sourced i io = 10 ma, v dd = 3.3 v 2.1 (1) - i io = 20 ma, v dd = 5 v 3.3 (1) - electrical characteristics STM8AF6213/23/23a/26 76/106 docid025118 rev 5 figure 24. typ. v ol @ v dd = 5 v (true open drain ports) figure 25. typ. v ol @ v dd = 3.3 v (true open drain ports) figure 26. typ. v ol @ v dd = 5 v (high sink ports) docid025118 rev 5 77/106 STM8AF6213/23/23a/26 electrical characteristics 103 figure 27. typ. v ol @ v dd = 3.3 v (high sink ports) figure 28. typ. v dd - v oh @ v dd = 5 v (standard ports) figure 29. typ. v dd - v oh @ v dd = 3.3 v (standard ports) electrical characteristics STM8AF6213/23/23a/26 78/106 docid025118 rev 5 figure 30. typ. v dd - v oh @ v dd = 5 v (high sink ports) figure 31. typ. v dd - v oh @ v dd = 3.3 v (high sink ports) docid025118 rev 5 79/106 STM8AF6213/23/23a/26 electrical characteristics 103 9.3.7 reset pin characteristics subject to general operating conditions for v dd and t a unless otherwise specified. figure 32. typical nrst v il and v ih vs v dd @ 4 temperatures table 51. nrst pin characteristics symbol parameter conditions min typ max unit v il(nrst) nrst input low level voltage (1) 1. data based on characterization results, not tested in production. --0.3- 0.3 x v dd v v ih(nrst) nrst input high level voltage (1) i ol = 2 ma 0.7 x v dd - v dd + 0.3 v ol(nrst) nrst output low level voltage (1) ---0.5 r pu(nrst) nrst pull-up resistor (2) 2. the r pu pull-up equivalent resistor is based on a resistive transistor. -305580k ? t ifp(nrst) nrst input filtered pulse (3) ---75 ns t infp(nrst) nrst input not filtered pulse duration (3) 3. data guaranteed by design, not tested in production. -500-- t op(nrst) nrst output pulse (3) -20--s electrical characteristics STM8AF6213/23/23a/26 80/106 docid025118 rev 5 figure 33. typical nrst pull-up resistance vs v dd @ 4 temperatures figure 34. typical nrst pull-up current vs v dd @ 4 temperatures the reset network shown in figure 35 protects the device against parasitic resets. the user must ensure that the level on the nrst pin can go below v il(nrst) max (see table 51: nrst pin characteristics ), otherwise the reset is not taken into account internally. for power consumption sensitive applications , the external reset capacitor value can be reduced to limit the charge/discharge current. if nrst signal is used to reset external circuitry, attention must be taken to the charge/ discharge time of the external capacitor to fulfill the external devices reset timing c onditions. minimum recommended capacity is 100 nf. docid025118 rev 5 81/106 STM8AF6213/23/23a/26 electrical characteristics 103 figure 35. recommended reset pin protection 9.3.8 spi serial peripheral interface unless otherwise specified, the parameters given in table 52 are derived from tests performed under ambient temperature, f master frequency and v dd supply voltage conditions. t master = 1/f master . refer to i/o port characteristics for more de tails on the input/output alternate function characteristics (nss, sck, mosi, miso). 0 6 y 9 ( [ w h u q d o u h v h w f l u f x l w r s w l r q d o ) 1 5 6 7 ) l o w h u 6 7 0 $ 9 ' ' 5 3 8 , q w h u q d o u h v h w table 52. spi characteristics symbol parameter conditions (1) min max unit f sck 1/t c(sck) spi clock frequency master mode 0 8 mhz slave mode 0 6 t r(sck ) t f(sck) spi clock rise and fall time capacitive load: ? c = 30 pf -25 ns t su(nss) (2) nss setup time slave mode 4 * t master - t h(nss) (2) nss hold time slave mode 70 - t w(sckh) (2) t w(sckl) (2) sck high and low time master mode t sck /2 - 15 t sck /2 + 15 t su(mi) (2) t su(si) (2) data input setup time master mode 5 - slave mode 5 - t h(mi) (2) t h(si) (2) data input hold time master mode 7 - slave mode 10 - t a(so) (2)(3) data output access time slave mode - 3* t master t dis(so) (2)(4) data output disable time slave mode 25 - t v(so) (2) data output valid time slave mode ? (after enable edge) -65 t v(mo) (2) data output valid time master mode ? (after enable edge) -36 electrical characteristics STM8AF6213/23/23a/26 82/106 docid025118 rev 5 figure 36. spi timing diagram - slave mode and cpha = 0 1. measurement points are made at cmos levels: 0.3 v dd and 0.7 v dd . t h(so) (2) data output hold time slave mode ? (after enable edge) 27 - ns t h(mo) (2) master mode ? (after enable edge) 11 - 1. parameters are given by selecting 10 mhz i/o output frequency. 2. values based on design simulation and/or characte rization results, and not tested in production. 3. min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data. 4. min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in hi-z. table 52. spi characteristics (continued) symbol parameter conditions (1) min max unit d l f 6 & . , q s x w 1 6 6 l q s x w w 6 8 1 6 6 w f 6 & . w k 1 6 6 & 3 + $ & 3 2 / & 3 + $ & 3 2 / w z 6 & . + w z 6 & . / w 9 6 2 w k 6 2 w u 6 & . w i 6 & . w g l v 6 2 w d 6 2 0 , 6 2 2 8 7 3 8 7 0 2 6 , , 1 3 8 7 0 6 % 2 8 7 % , 7 2 8 7 / 6 % 2 8 7 w v x 6 , w k 6 , 0 6 % , 1 % , 7 , 1 / 6 % , 1 docid025118 rev 5 83/106 STM8AF6213/23/23a/26 electrical characteristics 103 figure 37. spi timing diagram - slave mode and cpha = 1 1. measurement points are at cmos levels: 0.3 v dd and 0.7 v dd . figure 38. spi timing diagram - master mode (1) 1. measurement points are at cmos levels: 0.3 v dd and 0.7 v dd . d l e 1 6 6 l q s x w w 6 8 1 6 6 w f 6 & . w k 1 6 6 6 & . l q s x w & 3 + $ & 3 2 / & 3 + $ & 3 2 / w z 6 & . + w z 6 & . / w d 6 2 w y 6 2 w k 6 2 w u 6 & . w i 6 & . w g l v 6 2 0 , 6 2 2 8 7 3 8 7 0 2 6 , , 1 3 8 7 w v x 6 , w k 6 , 0 6 % 2 8 7 0 6 % , 1 % , 7 2 8 7 / 6 % 2 8 7 / 6 % , 1 % , 7 , 1 d l f 6 & . 2 x w s x w & 3 + $ 0 2 6 , 2 8 7 3 8 7 0 , 6 2 , 1 3 8 7 & 3 + $ / 6 % 2 8 7 / 6 % , 1 & 3 2 / & 3 2 / % , 7 2 8 7 1 6 6 l q s x w w f 6 & . w z 6 & . + w z 6 & . / w u 6 & . w i 6 & . w k 0 , + l j k 6 & . 2 x w s x w & 3 + $ & 3 + $ & 3 2 / & 3 2 / w v x 0 , w y 0 2 w k 0 2 0 6 % , 1 % , 7 , 1 0 6 % 2 8 7 electrical characteristics STM8AF6213/23/23a/26 84/106 docid025118 rev 5 9.3.9 i 2 c interface characteristics table 53. i 2 c characteristics symbol parameter standard mode i 2 cfast mode i 2 c (1) 1. f master , must be at least 8 mhz to achieve max fast i 2 c speed (400 khz) unit min (2) 2. data based on standard i 2 c protocol requirement, not tested in production max (2) min (2) max (2) t w(scll) scl clock low time 4.7 - 1.3 - s t w(sclh) scl clock high time 4.0 - 0.6 - t su(sda) sda setup time 250 - 100 - ns t h(sda) sda data hold time 0 (3) 3. the maximum hold time of the start condition has only to be met if the interface does not stretch the low time 3450 0 (4) 4. the device must internally provide a hold time of at least 300 ns for t he sda signal in order to bridge the undefined region of the falling edge of scl 900 (3) t r(sda) t r(scl) sda and scl rise time - 1000 - 300 t f(sda) t f(scl) sda and scl fall time - 300 - 300 t h(sta) start condition hold time 4.0 - 0.6 - s t su(sta) repeated start condition setup time 4.7 - 0.6 - t su(sto) stop condition setup time 4.0 - 0.6 - t w(sto:sta) stop to start condition time ? (bus free) 4.7 - 1.3 - t sp pulse width of spikes suppressed by the input filter 050 (5) 5. the minimum width of the spikes fi ltered by the analog filter is above t sp(max) 050ns c b capacitive load for each bus line - 400 - 400 pf docid025118 rev 5 85/106 STM8AF6213/23/23a/26 electrical characteristics 103 figure 39. typical application with i2c bus and timing diagram 1. measurement points are made at cmos levels: 0.3 x v dd and 0.7 x v dd . d l 9 6 7 $ 5 7 6 ' $ , e & e x v 9 ' ' 9 ' ' 6 7 0 6 ' $ 6 & / w i 6 ' $ w u 6 ' $ 6 & / w k 6 7 $ w z 6 & / + w z 6 & / / w v x 6 ' $ w u 6 & / w i 6 & / w k 6 ' $ 6 7 $ 5 7 5 ( 3 ( $ 7 ( ' 6 7 $ 5 7 w v x 6 7 $ w v x 6 7 2 6 7 2 3 w v x 6 7 $ 6 7 2 n ? n ? ? ? electrical characteristics STM8AF6213/23/23a/26 86/106 docid025118 rev 5 9.3.10 10-bit adc characteristics subject to general operating conditions for v dd , f master , and t a unless otherwise specified. table 54. adc characteristics symbol parameter conditions min typ max unit f adc adc clock frequency v dd = 3 to 5.5 v 1 - 4 mhz v dd = 4.5 to 5.5 v 1 - 6 v ain conversion voltage range (1) 1. during the sample time the input capacitance c ain (3 pf max) can be charged/ discharged by the external source. the internal resistance of the analog source must allow the capacitance to reach its final voltage level within t s . after the end of the sample time t s , changes of the analog input voltage have no effect on the conversion result. values for the sample clock t s depend on programming. - v ss - v dd v v bgref internal bandgap reference voltage v dd = 3 to 5.5 v 1.19 (2) 2. tested in production. 1.22 1.25 (2) v c adc internal sample and hold capacitor --3-pf t s (1) minimum sampling time f adc = 4mhz - 0.75 - s f adc = 6 mhz - 0.5 - t stab wakeup time from standby - - 7 - t conv minimum total conversion time including sampling time, 10-bit resolution f adc = 4 hz 3.5 s f adc = 6 mhz 2.33 -141/f adc docid025118 rev 5 87/106 STM8AF6213/23/23a/26 electrical characteristics 103 table 55. adc accuracy with rain < 10 k ? , v dd = 5 v symbol parameter conditions typ max (1) 1. max value is based on characte rization, not tested in production. unit |e t | total unadjusted error (2) 2. adc accuracy vs. negative injection current: injecti ng negative current on any of the analog input pins should be avoided as this significan tly reduces the accuracy of the conversion being performed on another analog input. it is recommended to add a schottky diode (pin to ground) to standard analog pins which may potentially inject negative current. any positive inje ction current within the limits specified for i inj(pin) and ? i inj(pin) in the i/o port pin characteristics se ction does not affect the adc accuracy. f adc = 2 mhz 1.6 3.5 lsb f adc = 4 mhz 2.2 4 f adc = 6 mhz 2.4 4.5 |e o | offset error (2) f adc = 2 mhz 1.1 2.5 f adc = 4 mhz 1.5 3 f adc = 6 mhz 1.8 3 |e g | gain error (2) f adc = 2 mhz 1.5 3 f adc = 4 mhz 2.1 3 f adc = 6 mhz 2.2 4 |e d | differential linearity error (2) f adc = 2 mhz 0.7 1.5 f adc = 4 mhz 0.7 1.5 f adc = 6 mhz 0.7 1.5 |e l | integral linearity error (2) f adc = 2 mhz 0.6 1.5 f adc = 4 mhz 0.8 2 f adc = 6 mhz 0.8 2 table 56. adc accuracy with rain < 10 k ? , v dd = 3.3 v symbol parameter conditions typ max (1) 1. max value is based on characte rization, not tested in production. unit |e t | total unadjusted error f adc = 2 mhz 1.6 3.5 lsb f adc = 4 mhz 1.9 4 |e o | offset error f adc = 2 mhz 12.5 f adc = 4 mhz 1.5 2.5 |e g | gain error f adc = 2 mhz 1.3 3 f adc = 4 mhz 23 |e d | differential linearity error f adc = 2 mhz 0.7 1 f adc = 4 mhz 0.7 1.5 |e l | integral linearity error f adc = 2 mhz 0.6 1.5 f adc = 4 mhz 0.8 2 electrical characteristics STM8AF6213/23/23a/26 88/106 docid025118 rev 5 figure 40. adc accuracy characteristics 1. example of an actual transfer curve 2. the ideal transfer curve 3. end point correlation line ? e t = total unadjusted error: maximum deviation betw een the actual and the ideal transfer curves. ? e o = offset error: deviation between the fi rst actual transition and the first ideal one. ? e g = gain error: deviation between the last ideal transition and the last actual one. ? e d = differential linearity error: maximum deviation between actual steps and the ideal one. ? e l = integral linearity error: maximum deviation between any actual transition an d the end point correlation line. figure 41. typical application with adc 1. legend: r ain = external resistance, c ain = capacitors, c samp = internal sample and hold capacitor. e o e g 1lsb ideal 1lsb ideal v dda v ssa ? 1024 ---------------------------------------- - = 1023 1022 1021 5 4 3 2 1 0 7 6 1234567 1021102210231024 (1) (2) e t e d e l (3) v dda v ssa 0 6 y 9 ^ d d? 5 $ , 1 & $ , 1 9 $ , 1 / e? 9 ' ' 9 7 9 9 7 9 & $ ' & , / ? ? $ e l w $ ' f r q y h u v l r q docid025118 rev 5 89/106 STM8AF6213/23/23a/26 electrical characteristics 103 9.3.11 emc characteristics susceptibility tests are perfor med on a sample basis during product characterization. functional ems (electromagnetic susceptibility) while executing a simple application (toggling 2 leds through i/o ports), the product is stressed by two electromagnetic events until a failure occurs (indicated by the leds). ? fesd : functional electrostatic discharge (posit ive and negative) is applied on all pins of the device until a functional disturbanc e occurs. this test conforms with the iec 61000-4-2 standard. ? ftb : a burst of fast transient voltage (p ositive and negative) is applied to v dd and v ss through a 100 pf capacitor, until a function al disturbance occurs. this test conforms with the iec 61000-4-4 standard. a device reset allows normal operations to be resumed. the test results are given in the table below based on the ems levels and classes defined in application note an1709. designing hardened software to avoid noise problems emc characterization and optimization are per formed at component level with a typical application environment and simplified mcu soft ware. it should be noted that good emc performance is highly dependent on the user application and the software in particular. therefore it is recommended that the user applies emc software optimization and prequalification tests in re lation with the emc level requested for his application. prequalification trials most of the common failures (unexpected reset and program counter corruption) can be recovered by applying a low state on the nr st pin or the oscillato r pins for 1 second. to complete these trials, esd stress can be applie d directly on the device, over the range of specification values. when unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see the application note reference an1015). table 57. ems data symbol parameter conditions level/class v fesd voltage limits to be applied on any i/o pin to induce a functional disturbance v dd ?? 3.3 v, t a ?? 25 c, ? f master ?? 16 mhz (hsi clock), ? conforms to iec 61000-4-2 2/b (1) 1. data obtained with hsi clock configuration, af ter applying hardware recommendations described in an2860 (emc guidelines for stm8s microcontrollers). v eftb fast transient voltage burst limits to be applied through 100 pf on v dd and v ss pins to induce a functional disturbance v dd ?? 3.3 v, t a ?? 25 c, ? f master ?? 16 mhz (hsi clock), ? conforms to iec 61000-4-4 4/a electrical characteristics STM8AF6213/23/23a/26 90/106 docid025118 rev 5 electromagnetic interference (emi) based on a simple application running on the product (toggling 2 leds through the i/o ports), the product is monitored in terms of em ission. this emission te st is in line with the norm iec 61967-2 which specifies the board and the loading of each pin. absolute maximum ratings (electrical sensitivity) based on three different tests (esd, dlu and lu) using specific measurement methods, the product is stressed to determine its perform ance in terms of electrical sensitivity. for more details, refer to the application note an1181. electrostatic discharge (esd) electrostatic discharges (one positive then one negative pulses separated by 1 second) are applied to the pins of each sample according to each pin combinati on. the sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). one model can be simulated: human body model. this test conforms to the jesd22-a114a/a115a standard. for more details, refer to the application note an1181. table 58. emi data symbol parameter conditions unit general conditions monitored frequency band max f hse /f cpu (1) 1. data based on characterization results, not tested in production. 16 mhz/ 8 mhz 16 mhz/ 16 mhz s emi peak level v dd ?? 5 v, ? t a ?? 25 c, ? lqfp32 package conforming to ? iec 61967-2 0.1 mhz to 30 mhz 5 5 dbv 30 mhz to 130 mhz 4 5 130 mhz to 1 ghz 5 5 emi level ? 2.5 2.5 level table 59. esd absolute maximum ratings symbol ratings conditions class maximum value (1) 1. data based on characterization results, not tested in production unit v esd(hbm) electrostatic discharge voltage ? (human body model) t a ?? 25c, conforming to jesd22-a114 3a 4000 v v esd(cdm) electrostatic discharge voltage ? (charge device model) t a ? 25c, conforming to jesd22-c101 3 500 v esd(mm) electrostatic discharge voltage ? (machine model) t a ? 25c, conforming to jesd22-a115 b 200 docid025118 rev 5 91/106 STM8AF6213/23/23a/26 electrical characteristics 103 static latch-up two complementary static te sts are required on six pa rts to assess the latch-up performance: ? a supply overvoltage (applied to each power supply pin), ? a current injection (applied to each input, output and configurable i/o pin) are performed on each sample. this test conforms to the eia/jesd 78 ic la tch-up standard. for more details, refer to the application note an1181. table 60. electrical sensitivities symbol parameter conditions class (1) 1. class description: a class is an stmi croelectronics internal specification. all its limits are higher than the jedec specifications, that means when a device belongs to class a it exceeds the jedec standard. b class strictly covers all the jede c criteria (international standard). lu static latch-up class t a ?? 25 c a t a ?? 85 c t a ?? 125 c t a ?? 150 c package information STM8AF6213/23/23a/26 92/106 docid025118 rev 5 10 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions a nd product status are available at: www.st.com . ecopack ? is an st trademark. 10.1 lqfp32 package information figure 42. lqfp32 - 32-pin, 7 x 7 mm low-profile quad flat package outline 1. drawing is not to scale. $ $ $ % % % ! , , + ! ! ! c b ' ! 5 ' % 0 , ! . % m m 3 % ! 4 ) . ' 0 , ! . % # 0 ) . ) $ % . 4 ) & ) # ! 4 ) / . c c c # 7 @ . & @ 7 e docid025118 rev 5 93/106 STM8AF6213/23/23a/26 package information 103 table 61. lqfp32 - 32-pin, 7 x 7 mm low-profile quad flat package mechanical data symbol millimeters inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. min typ max min typ max a - - 1.600 - - 0.0630 a1 0.050 - 0.150 0.0020 - 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.300 0.370 0.450 0.0118 0.0146 0.0177 c 0.090 - 0.200 0.0035 - 0.0079 d 8.800 9.000 9.200 0.3465 0.3543 0.3622 d1 6.800 7.000 7.200 0.2677 0.2756 0.2835 d3 - 5.600 - - 0.2205 - e 8.800 9.000 9.200 0.3465 0.3543 0.3622 e1 6.800 7.000 7.200 0.2677 0.2756 0.2835 e3 - 5.600 - - 0.2205 - e - 0.800 - - 0.0315 - l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 - 1.000 - - 0.0394 - k 03.57 03.57 ccc - - 0.100 - - 0.0039 package information STM8AF6213/23/23a/26 94/106 docid025118 rev 5 figure 43. lqfp32 - 32-pin, 7 x 7 mm low-profile quad flat package recommended footprint 1. dimensions are expr essed in millimeters. device marking the following figure gives an example of topsid e marking orientation versus pin 1 identifier location. figure 44. lqfp32 marking example (package top view) 6 ? & 0 ? 6 0 6 9 3 u r g x f w l g h q w l i l f d w l r q 3 l q l g h q w l i l h u 5 h y l v l r q f r g h ' d w h f r g h : 8 8 6 w d q g d u g 6 7 o r j r 9 9 9 9 9 9 9 9 9 9 9 9 docid025118 rev 5 95/106 STM8AF6213/23/23a/26 package information 103 10.2 tssop20 package information figure 45.tssop20 ? 20-lead thin shrink sma ll outline, 6.5 x 4.4 mm, 0.65 mm pitch, package outline 1. drawing is not to scale. table 62. tssop20 ? 20-lead thin shrink sm all outline, 6.5 x 4.4 mm, 0.65 mm pitch, package mechanical data symbol millimeters inches (1) min. typ. max. min. typ. max. a - - 1.200 - - 0.0472 a1 0.050 - 0.150 0.0020 - 0.0059 a2 0.800 1.000 1.050 0.0315 0.0394 0.0413 b 0.190 - 0.300 0.0075 - 0.0118 c 0.090 - 0.200 0.0035 - 0.0079 d (2) 6.400 6.500 6.600 0.2520 0.2559 0.2598 e 6.200 6.400 6.600 0.2441 0.2520 0.2598 e1 (3) 4.300 4.400 4.500 0.1693 0.1732 0.1772 e - 0.650 - - 0.0256 - l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 - 1.000 - - 0.0394 - 9 ! ? - % ? 6 # c , % % $ ! ! k e b ! , a a a 3 % ! 4 ) . ' 0 , ! . % # ' ! ' % 0 , ! . % m m 0 ) . ) $ % . 4 ) & ) # ! 4 ) / . package information STM8AF6213/23/23a/26 96/106 docid025118 rev 5 figure 46. tssop20 ? 20-lead thin shrink smal l outline, 6.5 x 4.4 mm, 0.65 mm pitch, package footprint 1. dimensions are expr essed in millimeters. k 0 - 8 0 - 8 aaa - - 0.100 - - 0.0039 1. values in inches are converted fr om mm and rounded to four decimal digits. 2. dimension ?d? does not include mold fl ash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.15mm per side. 3. dimension ?e1? does not include interlead flash or pr otrusions. interlead flash or protrusions shall not exceed 0.25mm per side. table 62. tssop20 ? 20-lead thin shrink sm all outline, 6.5 x 4.4 mm, 0.65 mm pitch, package mechanical data (continued) symbol millimeters inches (1) min. typ. max. min. typ. max. 9 ! ? & 0 ? 6 docid025118 rev 5 97/106 STM8AF6213/23/23a/26 package information 103 device marking the following figure gives an example of topsid e marking orientation versus pin 1 identifier location. figure 47. tssop20 marking example (package top view) 3 u r g x f w l g h q w l i l f d w l r q 3 l q l g h q w l i l h u 5 h y l v l r q f r g h ' d w h f r g h : 8 8 6 w d q g d u g 6 7 o r j r 9 9 9 9 9 9 9 9 9 0 6 9 package information STM8AF6213/23/23a/26 98/106 docid025118 rev 5 10.3 thermal characteristics the maximum chip junction temperature (t jmax ) must never exceed the values given in table 26: general operating conditions . t jmax , in degrees celsius, may be calculated using the following equation: t jmax = t amax + (p dmax x ? ja ) where: ?t amax is the maximum ambient temperature in ? c ? ? ja is the package junction-to-ambient thermal resistance in ?? c/w ?p dmax is the sum of p intmax and p i/omax (p dmax = p intmax + p i/omax ) ?p intmax is the product of i dd and v dd , expressed in watts. this is the maximum chip internal power. ?p i/omax represents the maximum power dissipation on output pins ? where: ? p i/omax = ?? (v ol *i ol ) + ? ((v dd -v oh )*i oh ), ? taking into account the actual v ol /i ol and v oh /i oh of the i/os at low and high level in the application. 10.3.1 reference document jesd51-2 integrated circuits thermal test method environment conditions - natural convection (still air). available from www.jedec.org. 10.3.2 selecting the product temperature range when ordering the microcontroller, the temperature range is specified in the order code (see section 11: ordering information ). the following example shows how to calculate the temperature range needed for a given application. table 63. thermal characteristics (1) 1. thermal resistances are based on jedec jesd51- 2 with 4-layer pcb in a natural convection environment. symbol parameter value unit ? ja thermal resistance junction-ambient ? tssop20 - 4 x 4 mm 110 c/w thermal resistance junction-ambient ? lqfp 32 - 7 x 7 mm 60 c/w docid025118 rev 5 99/106 STM8AF6213/23/23a/26 package information 103 assuming the following ap plication conditions: maximum ambient temperature t amax = 75 c (measured according to jesd51-2), i ddmax = 8 ma, v dd = 5 v maximum 20 i/os used at the same ti me in output at low level with: ? i ol = 8 ma, v ol = 0.4 v p intmax = 8 ma x 5 v= 400 mw p iomax = 20 x 8 ma x 0.4 v = 64 mw this gives: p intmax = 400 mw and p iomax 64 mw: p dmax = 400 mw + 64 mw thus: p dmax = 464 mw. using the values obtained in table 63: thermal characteristics on page 98 t jmax is calculated as follows: for lqfp32 60 c/w t jmax = 75 c + (60 c/w x464 mw) = 75 c + 27.8 c = 102.8 c this is within the range of th e suffix c version parts (-40 < t j < 125 c). parts must be ordered at least with the temperature range suffix c. ordering information STM8AF6213/23/23a/26 100/106 docid025118 rev 5 11 ordering information figure 48. STM8AF6213/23/23a/26 ordering information scheme (1) (2) 1. for a list of available options (e.g. memory size, package) and orderable part numbers or for further information on any aspect of this device, please go to www.st.com or contact the nearest st sales office. 2. parts marked as ?es?, ?e? or accompanied by an engineering sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at st charge. in no event, st will be liable for any customer usage of these engineering samples in production. st quality has to be cont acted prior to any decisi on to use these engineering samples to run qualification activity. stm8a f 62 2 3 i p c a u product class 8-bit automotive microcontroller program memory size 1 = 4 kbyte 2 = 8 kbyte number of adc analog inputs blank = 5 analog inputs a = 7 analog inputs example: device family 62 = lin only program memory type f = flash + eeprom temperature range a = -40 to 85 c c = -40 to 125 c d = -40 to 150 c pin count 3 = 20 pins 6 = 32 pins packing y = tray u = tube x = tape and reel compliant with eia 481-c hsi accuracy blank = 5% i = 3% package type t = lqfp p = tssop docid025118 rev 5 101/106 STM8AF6213/23/23a/26 stm8 development tools 103 12 stm8 development tools development tools for the stm8 microcontrollers include the full-featured stice emulation system supported by a complete software tool package including c compiler, assembler and integrated development environment with high-l evel language debugger. in addition, the stm8 is to be supported by a complete range of tools including starter kits, evaluation boards and a low-cost in-circuit debugger/programmer. 12.1 emulation and in-c ircuit debugging tools the stice emulation system offers a complete range of emulation and in-circuit debugging features on a platform that is designed for vers atility and cost-effectiveness. in addition, the stm8 application development is supported by a low-cost in-circuit debugger/programmer. the stice is the fourth generation of full-fe atured emulators from stmicroelectronics. it offers new advanced debugging capabilities including coverage to help de tect and eliminate bottlenecks in application execution and dead code when fine tuning an application. in addition, stice offers in-circuit debuggi ng and programming of stm8a microcontrollers via the stm8 single wire interface module (swim), which allows non-intrusive debugging of an application while it runs on the target microcontroller. for improved cost effectiveness, stice is based on a modular design that allows you to order exactly what you need to meet your development requirements and to adapt your emulation system to support existing and future st microcontrollers. 12.1.1 stice key features ? occurrence and time profiling and code coverage analysis (new features) ? advanced breakpoints with up to 4 levels of conditions ? data breakpoints ? program and data trace recording up to 128 kb records ? read/write on-the-fly of memory during emulation ? in-circuit debugging/prog ramming via swim protocol ? 8-bit probe analyzer ? 1 input and 2 output triggers ? power supply follower managing application voltages between 1.62 to 5.5 v ? modularity that allows you to specify the components you need to meet your development requirements and adapt to future requirements. ? supported by free software tools that include integrated development environment (ide), programming software interface and assembler for stm8. stm8 development tools STM8AF6213/23/23a/26 102/106 docid025118 rev 5 12.2 software tools stm8 development tools are supported by a complete, free software package from ? stmicroelectronics that includes st vis ual develop (stvd) ide and the st visual ? programmer (stvp) software interface. stvd pr ovides seamless integr ation of the cosmic and raisonance c co mpilers for stm8. 12.2.1 stm8 toolset the stm8 toolset with stvd integrated development environment and stvp programming software is available for free download at www.st.com. this package includes: st visual develop full-featured integrated development environment from stmicroelectronics, featuring: ? seamless integration of c and asm toolsets ? full-featured debugger ? project management ? syntax highlighting editor ? integrated programming interface ? support of advanced emulatio n features for stice such as code profiling and coverage st visual programmer (stvp) easy-to-use, unlimited graphical interface allo wing read, write and verify of your stm8 microcontroller flash program memory, data eeprom and option bytes. stvp also offers project mode for saving programming conf igurations and automating programming sequences. 12.2.2 c and assembly toolchains control of c and assembly toolchains is seam lessly integrat ed into the stvd integrated development environment, making it possible to configure and control the building of the application directly from an ea sy-to-use graphical interface. available toolchains include: cosmic c compiler for stm8 all compilers are available in free version with a limited code size depending on the compiler. for more information, refer to ww w.cosmic-software.com, www.raisonance.com, and www.iar.com. stm8 assembler linker free assembly toolchain included in the stm8 toolset, which allows the users to assemble and link your application source code. docid025118 rev 5 103/106 STM8AF6213/23/23a/26 stm8 development tools 103 12.3 programming tools during the development cycle, stice provides in-circuit pr ogramming of the stm8 flash microcontroller on the user application board vi a the swim protocol. additional tools include a low-cost in-circuit programmer as well as st socket boards, which provide dedicated programming platforms with sockets for programming the stm8. for production environments, programmers will include a comp lete range of gang and automated programming solutions from thir d-party tool developers already supplying programmers for the stm8 family. revision history STM8AF6213/23/23a/26 104/106 docid025118 rev 5 13 revision history table 64. document revision history date revision changes 11-oct-2013 1 initial release. 16-dec-2013 2 changed the document status to production data. updated figure: stm8af6223pxax tssop20 pinout to add spi_nss to pd4, tli to pd2, and change remap function on pb5 from tim5_bkin to tim1_bkin. updated table: stm8af6223pxax tssop20 pin description to add spi_nss to pd4 and tli to pd2. updated table: stm8af6223 tssop20 pin description and table: lqfp32 pin descriptio n. updated afr2 definition in table: stm8af6223pxax alternate function remapping bits [7:2] for 20-pin packages . removed the remapping option on pa3 for afr[1:0]=10 in table: stm8af6223pxax alternate function remapping bits [1:0] for 20-pin packages . added note and removed remapping option on pa3 for afr[1:0]=11 in table: stm8af6223 alternate function remapping bits [1:0] for 20-pin packages . updated afr2 definition in stm8af6223 alternate function remapping bits [7:2] for 20-pin packages. added the note below table: stm8af6226t alternate function remapping bits [1:0] for 32-pin packages . updated table: i2c characteristics to modify t h(sda) and add t sp . updated section: c assembly toolchains . 03-apr-2014 3 replaced stm8af6226t by stm8af6226 part number. added stm8af6223a part number to cover stm8af6223pxax order codes. removed linuart alternate function for pa3 in table: stm8af6223pxax tssop20 pin description . removed note 3 for i dd(ah) in table: total current consumption in active halt mode at vdd = 5 v . updated the remapping option on pa3 for afr[1:0]=11 in table: stm8af6223 alternate function remapping bits [1:0] for 20-pin packages . updated notes related to t ret minimum value in table: data memory . updated table: esd absolute maximum ratings. added notes related to protrusions and gate burrs for d and e1 dimensions in table: 20-pin, 4.40 mm body, 0.65 mm pitch mechanical data . docid025118 rev 5 105/106 STM8AF6213/23/23a/26 revision history 105 10-jul-2014 4 extended the applicability to STM8AF6213 devices. updated the program memo ry feature, the power management, and the clock management features on the cover page. added the table in section: memory map . updated the figure: f cpumax versus v dd in section: operating conditions. updated section: ordering information . 26-jun-2015 5 added: ? the footnote about the inrush current below table 27: operating conditions at power-up/power-down , ? figure 44: lqfp32 marking example (package top view) , ? figure 47: tssop20 marking example (package top view) . updated ? lin standard version, ? the register label for linuart block in table 11: general hardware register map , ? the power dissipation in table 26: general operating conditions , ? table 41: hsi oscillator characteristics for hsi oscillator accuracy, ? the standard for emi in electromagnetic interference (emi) , ? figure 48: STM8AF6213/23/23a/26 ordering information scheme(1) (2) to add hsi accuracy. moved section 10.3: thermal characteristics to section 10: package information . table 64. document revision history (continued) date revision changes STM8AF6213/23/23a/26 106/106 docid025118 rev 5 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant in formation on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of o rder acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2015 stmicroelectronics ? all rights reserved |
Price & Availability of STM8AF6213
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |